The PMU architecture for the Hygon Dhyana CPU is similar to the AMD
family 17h one. So add Hygon Dhyana support in vpmu_arch_initialise
and vpmu_init by using the code path of AMD.
Since current Xen vPMU still not support Zen(0x17), so add both 0x17
and 0x18 support by using the 0x15's case in amd_vpmu_init, for 0x17
and 0x18 have the same performance event select and counter MSRs as
0x15 has.
Signed-off-by: Pu Wen <pu...@hygon.cn>
---
xen/arch/x86/cpu/vpmu.c | 2 ++
xen/arch/x86/cpu/vpmu_amd.c | 2 ++
2 files changed, 4 insertions(+)
diff --git a/xen/arch/x86/cpu/vpmu.c b/xen/arch/x86/cpu/vpmu.c
index 13da7d0..f679e79 100644
--- a/xen/arch/x86/cpu/vpmu.c
+++ b/xen/arch/x86/cpu/vpmu.c
@@ -459,6 +459,7 @@ static int vpmu_arch_initialise(struct vcpu *v)
switch ( vendor )
{
case X86_VENDOR_AMD:
+ case X86_VENDOR_HYGON:
ret = svm_vpmu_initialise(v);
break;
@@ -876,6 +877,7 @@ static int __init vpmu_init(void)
switch ( vendor )
{
case X86_VENDOR_AMD:
+ case X86_VENDOR_HYGON:
if ( amd_vpmu_init() )
vpmu_mode = XENPMU_MODE_OFF;
break;
diff --git a/xen/arch/x86/cpu/vpmu_amd.c b/xen/arch/x86/cpu/vpmu_amd.c
index 5efc39b..c9abe6e 100644
--- a/xen/arch/x86/cpu/vpmu_amd.c
+++ b/xen/arch/x86/cpu/vpmu_amd.c
@@ -545,6 +545,8 @@ int __init amd_vpmu_init(void)
switch ( current_cpu_data.x86 )
{
case 0x15:
+ case 0x17:
+ case 0x18:
num_counters = F15H_NUM_COUNTERS;
counters = AMD_F15H_COUNTERS;
ctrls = AMD_F15H_CTRLS;
--
2.7.4
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