+
+enum pm_api_id {
+ /* Miscellaneous API functions: */
+ PM_GET_API_VERSION = 1, /* Do not change or move */
+ PM_SET_CONFIGURATION,
+ PM_GET_NODE_STATUS,
+ PM_GET_OP_CHARACTERISTIC,
+ PM_REGISTER_NOTIFIER,
+ /* API for suspending of PUs: */
+ PM_REQ_SUSPEND,
+ PM_SELF_SUSPEND,
+ PM_FORCE_POWERDOWN,
+ PM_ABORT_SUSPEND,
+ PM_REQ_WAKEUP,
+ PM_SET_WAKEUP_SOURCE,
+ PM_SYSTEM_SHUTDOWN,
+ /* API for managing PM slaves: */
+ PM_REQ_NODE,
+ PM_RELEASE_NODE,
+ PM_SET_REQUIREMENT,
+ PM_SET_MAX_LATENCY,
+ /* Direct control API functions: */
+ PM_RESET_ASSERT,
+ PM_RESET_GET_STATUS,
+ PM_MMIO_WRITE,
+ PM_MMIO_READ,
+ PM_INIT,
+ PM_FPGA_LOAD,
+ PM_FPGA_GET_STATUS,
+ PM_GET_CHIPID,
+ /* ID 25 is been used by U-boot to process secure boot images */
+ /* Secure library generic API functions */
+ PM_SECURE_SHA = 26,
+ PM_SECURE_RSA,
+ /* Pin control API functions */
+ PM_PINCTRL_REQUEST,
+ PM_PINCTRL_RELEASE,
+ PM_PINCTRL_GET_FUNCTION,
+ PM_PINCTRL_SET_FUNCTION,
+ PM_PINCTRL_CONFIG_PARAM_GET,
+ PM_PINCTRL_CONFIG_PARAM_SET,
+ /* PM IOCTL API */
+ PM_IOCTL,
+ /* API to query information from firmware */
+ PM_QUERY_DATA,
+ /* Clock control API functions */
+ PM_CLOCK_ENABLE,
+ PM_CLOCK_DISABLE,
+ PM_CLOCK_GETSTATE,
+ PM_CLOCK_SETDIVIDER,
+ PM_CLOCK_GETDIVIDER,
+ PM_CLOCK_SETRATE,
+ PM_CLOCK_GETRATE,
+ PM_CLOCK_SETPARENT,
+ PM_CLOCK_GETPARENT,
+ PM_API_MAX
+};
+
+enum pm_node_id {
+ NODE_RPU = 6,
+ NODE_RPU_0,
+ NODE_RPU_1,
+ NODE_GPU_PP_0 = 20,
+ NODE_GPU_PP_1,
+ NODE_USB_0,
+ NODE_USB_1,
+ NODE_TTC_0,
+ NODE_TTC_1,
+ NODE_TTC_2,
+ NODE_TTC_3,
+ NODE_SATA,
+ NODE_ETH_0,
+ NODE_ETH_1,
+ NODE_ETH_2,
+ NODE_ETH_3,
+ NODE_UART_0,
+ NODE_UART_1,
+ NODE_SPI_0,
+ NODE_SPI_1,
+ NODE_I2C_0,
+ NODE_I2C_1,
+ NODE_SD_0,
+ NODE_SD_1,
+ NODE_DP,
+ NODE_GDMA,
+ NODE_ADMA,
+ NODE_NAND,
+ NODE_QSPI,
+ NODE_GPIO,
+ NODE_CAN_0,
+ NODE_CAN_1,
+ NODE_AFI,
+ NODE_APLL,
+ NODE_VPLL,
+ NODE_DPLL,
+ NODE_RPLL,
+ NODE_IOPLL,
+ NODE_DDR,
+ NODE_IPI_APU,
+ NODE_IPI_RPU_0,
+ NODE_GPU,
+ NODE_PCIE,
+ NODE_PCAP,
+ NODE_RTC,
+};
+
+/**
+ * @XST_PM_SUCCESS: Success
+ * @XST_PM_INTERNAL: Unexpected error
+ * @XST_PM_CONFLICT: Conflicting requirements
+ * @XST_PM_NO_ACCESS: Access rights violation
+ * @XST_PM_INVALID_NODE: Does not apply to node passed as argument
+ * @XST_PM_DOUBLE_REQ: Duplicate request
+ * @XST_PM_ABORT_SUSPEND: Target has aborted suspend
+ */
+enum pm_ret_status {
+ XST_PM_SUCCESS = 0,
+ XST_PM_INTERNAL = 2000,
+ XST_PM_CONFLICT,
+ XST_PM_NO_ACCESS,
+ XST_PM_INVALID_NODE,
+ XST_PM_DOUBLE_REQ,
+ XST_PM_ABORT_SUSPEND,
+};
+
+enum pm_reset {
+ XILPM_RESET_START = 999,
+ XILPM_RESET_PCIE_CFG,
+ XILPM_RESET_PCIE_BRIDGE,
+ XILPM_RESET_PCIE_CTRL,
+ XILPM_RESET_DP,
+ XILPM_RESET_SWDT_CRF,
+ XILPM_RESET_AFI_FM5,
+ XILPM_RESET_AFI_FM4,
+ XILPM_RESET_AFI_FM3,
+ XILPM_RESET_AFI_FM2,
+ XILPM_RESET_AFI_FM1,
+ XILPM_RESET_AFI_FM0,
+ XILPM_RESET_GDMA,
+ XILPM_RESET_GPU_PP1,
+ XILPM_RESET_GPU_PP0,
+ XILPM_RESET_GPU,
+ XILPM_RESET_GT,
+ XILPM_RESET_SATA,
+ XILPM_RESET_ACPU3_PWRON,
+ XILPM_RESET_ACPU2_PWRON,
+ XILPM_RESET_ACPU1_PWRON,
+ XILPM_RESET_ACPU0_PWRON,
+ XILPM_RESET_APU_L2,
+ XILPM_RESET_ACPU3,
+ XILPM_RESET_ACPU2,
+ XILPM_RESET_ACPU1,
+ XILPM_RESET_ACPU0,
+ XILPM_RESET_DDR,
+ XILPM_RESET_APM_FPD,
+ XILPM_RESET_SOFT,
+ XILPM_RESET_GEM0,
+ XILPM_RESET_GEM1,
+ XILPM_RESET_GEM2,
+ XILPM_RESET_GEM3,
+ XILPM_RESET_QSPI,
+ XILPM_RESET_UART0,
+ XILPM_RESET_UART1,
+ XILPM_RESET_SPI0,
+ XILPM_RESET_SPI1,
+ XILPM_RESET_SDIO0,
+ XILPM_RESET_SDIO1,
+ XILPM_RESET_CAN0,
+ XILPM_RESET_CAN1,
+ XILPM_RESET_I2C0,
+ XILPM_RESET_I2C1,
+ XILPM_RESET_TTC0,
+ XILPM_RESET_TTC1,
+ XILPM_RESET_TTC2,
+ XILPM_RESET_TTC3,
+ XILPM_RESET_SWDT_CRL,
+ XILPM_RESET_NAND,
+ XILPM_RESET_ADMA,
+ XILPM_RESET_GPIO,
+ XILPM_RESET_IOU_CC,
+ XILPM_RESET_TIMESTAMP,
+ XILPM_RESET_RPU_R50,
+ XILPM_RESET_RPU_R51,
+ XILPM_RESET_RPU_AMBA,
+ XILPM_RESET_OCM,
+ XILPM_RESET_RPU_PGE,
+ XILPM_RESET_USB0_CORERESET,
+ XILPM_RESET_USB1_CORERESET,
+ XILPM_RESET_USB0_HIBERRESET,
+ XILPM_RESET_USB1_HIBERRESET,
+ XILPM_RESET_USB0_APB,
+ XILPM_RESET_USB1_APB,
+ XILPM_RESET_IPI,
+ XILPM_RESET_APM_LPD,
+ XILPM_RESET_RTC,
+ XILPM_RESET_SYSMON,
+ XILPM_RESET_AFI_FM6,
+ XILPM_RESET_LPD_SWDT,
+ XILPM_RESET_FPD,
+ XILPM_RESET_RPU_DBG1,
+ XILPM_RESET_RPU_DBG0,
+ XILPM_RESET_DBG_LPD,
+ XILPM_RESET_DBG_FPD,
+ XILPM_RESET_APLL,
+ XILPM_RESET_DPLL,
+ XILPM_RESET_VPLL,
+ XILPM_RESET_IOPLL,
+ XILPM_RESET_RPLL,
+ XILPM_RESET_GPO3_PL_0,
+ XILPM_RESET_GPO3_PL_1,
+ XILPM_RESET_GPO3_PL_2,
+ XILPM_RESET_GPO3_PL_3,
+ XILPM_RESET_GPO3_PL_4,
+ XILPM_RESET_GPO3_PL_5,
+ XILPM_RESET_GPO3_PL_6,
+ XILPM_RESET_GPO3_PL_7,
+ XILPM_RESET_GPO3_PL_8,
+ XILPM_RESET_GPO3_PL_9,
+ XILPM_RESET_GPO3_PL_10,
+ XILPM_RESET_GPO3_PL_11,
+ XILPM_RESET_GPO3_PL_12,
+ XILPM_RESET_GPO3_PL_13,
+ XILPM_RESET_GPO3_PL_14,
+ XILPM_RESET_GPO3_PL_15,
+ XILPM_RESET_GPO3_PL_16,
+ XILPM_RESET_GPO3_PL_17,
+ XILPM_RESET_GPO3_PL_18,
+ XILPM_RESET_GPO3_PL_19,
+ XILPM_RESET_GPO3_PL_20,
+ XILPM_RESET_GPO3_PL_21,
+ XILPM_RESET_GPO3_PL_22,
+ XILPM_RESET_GPO3_PL_23,
+ XILPM_RESET_GPO3_PL_24,
+ XILPM_RESET_GPO3_PL_25,
+ XILPM_RESET_GPO3_PL_26,
+ XILPM_RESET_GPO3_PL_27,
+ XILPM_RESET_GPO3_PL_28,
+ XILPM_RESET_GPO3_PL_29,
+ XILPM_RESET_GPO3_PL_30,
+ XILPM_RESET_GPO3_PL_31,
+ XILPM_RESET_RPU_LS,
+ XILPM_RESET_PS_ONLY,
+ XILPM_RESET_PL,
+ XILPM_RESET_END
+};
+
extern bool zynqmp_eemi(struct cpu_user_regs *regs);
#endif /* __ASM_ARM_PLATFORMS_ZYNQMP_H */
