This is a straight backport of c/s 28d9a9a2d41759b9e5163037b759ac557aea767c
but with a different justification.
Dom0 may have superpages (e.g. initial P2M), and may be shadowed
(e.g. PV-L1TF). Because of this incorrect check, when PV superpages are
disallowed (which is the security supported configuration), attempting to
shadow the P2M with its superpages still intact will fail. A #PF will be
handed back to the kernel, rather than the superpage being splintered and
shadowed.
Signed-off-by: Andrew Cooper <andrew.coop...@citrix.com>
---
CC: Jan Beulich <jbeul...@suse.com>
CC: Wei Liu <wei.l...@citrix.com>
---
xen/include/asm-x86/guest_pt.h | 12 +++++++-----
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/xen/include/asm-x86/guest_pt.h b/xen/include/asm-x86/guest_pt.h
index 72126d5..08031c8 100644
--- a/xen/include/asm-x86/guest_pt.h
+++ b/xen/include/asm-x86/guest_pt.h
@@ -205,15 +205,17 @@ static inline guest_l4e_t guest_l4e_from_gfn(gfn_t gfn,
u32 flags)
static inline bool guest_can_use_l2_superpages(const struct vcpu *v)
{
/*
+ * PV guests use Xen's paging settings. Being 4-level, 2M
+ * superpages are unconditionally supported.
+ *
* The L2 _PAGE_PSE bit must be honoured in HVM guests, whenever
* CR4.PSE is set or the guest is in PAE or long mode.
* It's also used in the dummy PT for vcpus with CR0.PG cleared.
*/
- return (is_pv_vcpu(v)
- ? opt_allow_superpage
- : (GUEST_PAGING_LEVELS != 2
- || !hvm_paging_enabled(v)
- || (v->arch.hvm_vcpu.guest_cr[4] & X86_CR4_PSE)));
+ return (is_pv_vcpu(v) ||
+ GUEST_PAGING_LEVELS != 2 ||
+ !hvm_paging_enabled(v) ||
+ (v->arch.hvm_vcpu.guest_cr[4] & X86_CR4_PSE));
}
static inline bool guest_can_use_l3_superpages(const struct domain *d)
--
2.1.4
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