Hi,
On 06/08/18 19:35, Oleksandr Tyshchenko wrote:
From: Oleksandr Tyshchenko <oleksandr_tyshche...@epam.com>
Add support for Renesas "Stout" development board based on
R-Car H2 SoC which has SCIFA compatible UART.
Actually existing SCIF UART support (debug-scif.inc) and
newly added SCIFA UART support (debug-scifa.inc) differ only
in registers offsets.
In that case, could we just extend debug-scif.inc?
Signed-off-by: Oleksandr Tyshchenko <oleksandr_tyshche...@epam.com>
CC: Stefano Stabellini <sstabell...@kernel.org>
CC: Julien Grall <julien.gr...@arm.com>
---
docs/misc/arm/early-printk.txt | 3 ++-
xen/arch/arm/Rules.mk | 1 +
xen/arch/arm/arm32/debug-scifa.inc | 51 ++++++++++++++++++++++++++++++++++++++
3 files changed, 54 insertions(+), 1 deletion(-)
create mode 100644 xen/arch/arm/arm32/debug-scifa.inc
diff --git a/docs/misc/arm/early-printk.txt b/docs/misc/arm/early-printk.txt
index f765f59..f1b55d3 100644
--- a/docs/misc/arm/early-printk.txt
+++ b/docs/misc/arm/early-printk.txt
@@ -39,12 +39,13 @@ the name of the machine:
- fastmodel: printk on ARM Fastmodel software emulators
- hikey960: printk with pl011 with Hikey 960
- juno: printk with pl011 on Juno platform
- - lager: printk with SCIF0 on Renesas R-Car H2 processors
+ - lager: printk with SCIF0 on Renesas Lager board (R-Car H2 processor)
Why this change?
- midway: printk with the pl011 on Calxeda Midway processors
- mvebu: printk with the MVEBU for Marvell Armada 3700 SoCs
- omap5432: printk with UART3 on TI OMAP5432 processors
- rcar3: printk with SCIF2 on Renesas R-Car Gen3 processors
- seattle: printk with pl011 for AMD Seattle processor
+ - stout: printk with SCIFA0 on Renesas Stout board (R-Car H2 processor)
I have started to look at porting that to Kconfig ealyprintk and it is a
massive pain. So I would tend to prefer if we avoid adding more
convenience alias and instead document on the wiki page how to use
earlyprintk for that.
- sun6i: printk with 8250 on Allwinner A31 processors
- sun7i: printk with 8250 on Allwinner A20 processors
- thunderx: printk with pl011 for Cavium ThunderX processor
diff --git a/xen/arch/arm/Rules.mk b/xen/arch/arm/Rules.mk
index f264592..e011f8b 100644
--- a/xen/arch/arm/Rules.mk
+++ b/xen/arch/arm/Rules.mk
@@ -40,6 +40,7 @@ EARLY_PRINTK_mvebu := mvebu,0xd0012000
EARLY_PRINTK_omap5432 := 8250,0x48020000,2
EARLY_PRINTK_rcar3 := scif,0xe6e88000
EARLY_PRINTK_seattle := pl011,0xe1010000
+EARLY_PRINTK_stout := scifa,0xe6c40000
EARLY_PRINTK_sun6i := 8250,0x01c28000,2
EARLY_PRINTK_sun7i := 8250,0x01c28000,2
EARLY_PRINTK_thunderx := pl011,0x87e024000000
diff --git a/xen/arch/arm/arm32/debug-scifa.inc
b/xen/arch/arm/arm32/debug-scifa.inc
new file mode 100644
index 0000000..b5e60db
--- /dev/null
+++ b/xen/arch/arm/arm32/debug-scifa.inc
@@ -0,0 +1,51 @@
+/*
+ * xen/arch/arm/arm32/debug-scifa.inc
+ *
+ * SCIFA specific debug code
+ *
+ * Oleksandr Tyshchenko <oleksandr_tyshche...@epam.com>
+ * Copyright (C) 2018 EPAM Systems Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <asm/scif-uart.h>
+
+/*
+ * SCIFA UART wait UART to be ready to transmit
+ * rb: register which contains the UART base address
+ * rc: scratch register
+ */
+.macro early_uart_ready rb rc
+1:
+ ldrh \rc, [\rb, #SCIFA_SCASSR] /* <- SCASSR (status register) */
+ tst \rc, #SCASSR_TDFE /* Check TDFE bit */
+ beq 1b /* Wait for the UART to be ready */
+.endm
+
+/*
+ * SCIFA UART transmit character
+ * rb: register which contains the UART base address
+ * rt: register which contains the character to transmit
+ */
+.macro early_uart_transmit rb rt
+ strb \rt, [\rb, #SCIFA_SCAFTDR] /* -> SCAFTDR (data
register) */
+ ldrh \rt, [\rb, #SCIFA_SCASSR] /* <- SCASSR
(status register) */
+ and \rt, \rt, #(~(SCASSR_TEND | SCASSR_TDFE)) /* Clear TEND and
TDFE bits */
+ strh \rt, [\rb, #SCIFA_SCASSR] /* -> SCASSR
(status register) */
+.endm
+
+/*
+ * Local variables:
+ * mode: ASM
+ * indent-tabs-mode: nil
+ * End:
+ */
Cheers,
--
Julien Grall
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