Add a XEN infix, to properly distinguish it from the CPUID feature flag (leaf 6 EAX bit 2).
Signed-off-by: Jan Beulich <[email protected]> --- Question is whether we still need opt_arat (and the command line option), or whether we could go directly from the CPUID bit (overriding it to on for older AMD [and Hygon?] CPUs). Or whether to have opt_arat affect the (host) CPU policy directly. --- a/xen/arch/x86/acpi/cpu_idle.c +++ b/xen/arch/x86/acpi/cpu_idle.c @@ -109,7 +109,7 @@ void (*__read_mostly lapic_timer_on)(voi bool lapic_timer_init(void) { - if ( boot_cpu_has(X86_FEATURE_ARAT) ) + if ( boot_cpu_has(X86_FEATURE_XEN_ARAT) ) { lapic_timer_off = lapic_timer_nop; lapic_timer_on = lapic_timer_nop; @@ -1463,7 +1463,7 @@ static void amd_cpuidle_init(struct acpi if ( !vendor_override ) { - if ( !boot_cpu_has(X86_FEATURE_ARAT) ) + if ( !boot_cpu_has(X86_FEATURE_XEN_ARAT) ) hpet_broadcast_init(); if ( !lapic_timer_init() ) --- a/xen/arch/x86/cpu/amd.c +++ b/xen/arch/x86/cpu/amd.c @@ -1355,7 +1355,7 @@ static void cf_check init_amd(struct cpu * running in deep C states. */ if ( opt_arat && c->x86 > 0x11 ) - __set_bit(X86_FEATURE_ARAT, c->x86_capability); + __set_bit(X86_FEATURE_XEN_ARAT, c->x86_capability); /* * Prior to Family 0x14, perf counters are not reset during warm reboot. --- a/xen/arch/x86/cpu/hygon.c +++ b/xen/arch/x86/cpu/hygon.c @@ -76,7 +76,7 @@ static void cf_check init_hygon(struct c /* Hygon processors have APIC timer running in deep C states. */ if (opt_arat) - __set_bit(X86_FEATURE_ARAT, c->x86_capability); + __set_bit(X86_FEATURE_XEN_ARAT, c->x86_capability); if (cpu_has(c, X86_FEATURE_EFRO)) { rdmsrl(MSR_K8_HWCR, value); --- a/xen/arch/x86/cpu/intel.c +++ b/xen/arch/x86/cpu/intel.c @@ -668,7 +668,7 @@ static void cf_check init_intel(struct c if ( opt_arat && ( c->cpuid_level >= 0x00000006 ) && ( cpuid_eax(0x00000006) & (1u<<2) ) ) - __set_bit(X86_FEATURE_ARAT, c->x86_capability); + __set_bit(X86_FEATURE_XEN_ARAT, c->x86_capability); if ((opt_cpu_info && !(c->apicid & (c->x86_num_siblings - 1))) || c == &boot_cpu_data ) --- a/xen/arch/x86/cpu/mwait-idle.c +++ b/xen/arch/x86/cpu/mwait-idle.c @@ -1633,7 +1633,7 @@ static int __init mwait_idle_probe(void) icpu = id->driver_data; cpuidle_state_table = icpu->state_table; - if (boot_cpu_has(X86_FEATURE_ARAT)) + if (boot_cpu_has(X86_FEATURE_XEN_ARAT)) lapic_timer_reliable_states = LAPIC_TIMER_ALWAYS_RELIABLE; pr_debug(PREFIX "v" MWAIT_IDLE_VERSION " model %#x\n", @@ -1792,7 +1792,7 @@ int __init mwait_idle_init(struct notifi return -ENODEV; err = mwait_idle_probe(); - if (!err && !boot_cpu_has(X86_FEATURE_ARAT)) { + if (!err && !boot_cpu_has(X86_FEATURE_XEN_ARAT)) { hpet_broadcast_init(); if (xen_cpuidle < 0 && !hpet_broadcast_is_available()) err = -ENODEV; --- a/xen/arch/x86/include/asm/cpufeatures.h +++ b/xen/arch/x86/include/asm/cpufeatures.h @@ -13,7 +13,7 @@ /* Synthetic features */ XEN_CPUFEATURE(CONSTANT_TSC, X86_SYNTH( 0)) /* TSC ticks at a constant rate */ XEN_CPUFEATURE(NONSTOP_TSC, X86_SYNTH( 1)) /* TSC does not stop in C states */ -XEN_CPUFEATURE(ARAT, X86_SYNTH( 2)) /* Always running APIC timer */ +XEN_CPUFEATURE(XEN_ARAT, X86_SYNTH( 2)) /* Xen may utilize always running APIC timer */ XEN_CPUFEATURE(ARCH_PERFMON, X86_SYNTH( 3)) /* Intel Architectural PerfMon */ XEN_CPUFEATURE(TSC_RELIABLE, X86_SYNTH( 4)) /* TSC is known to be reliable */ XEN_CPUFEATURE(XTOPOLOGY, X86_SYNTH( 5)) /* cpu topology enum extensions */ --- a/xen/arch/x86/time.c +++ b/xen/arch/x86/time.c @@ -2642,7 +2642,7 @@ static int _disable_pit_irq(bool init) * XXX dom0 may rely on RTC interrupt delivery, so only enable * hpet_broadcast if FSB mode available or if force_hpet_broadcast. */ - if ( cpuidle_using_deep_cstate() && !boot_cpu_has(X86_FEATURE_ARAT) ) + if ( cpuidle_using_deep_cstate() && !boot_cpu_has(X86_FEATURE_XEN_ARAT) ) { init ? hpet_broadcast_init() : hpet_broadcast_resume(); if ( !hpet_broadcast_is_available() )
