Hi Julien, On 29.07.25 17:05, Julien Grall wrote: > Hi, > > On 24/07/2025 15:57, Leonid Komarianskyi wrote: >> To properly deactivate guest interrupts and allow them to be retriggered >> after the initial trigger, the LR needs to be updated. The current >> implementation ignores interrupts outside the range specified by the mask >> 0x3FF, which only covers IRQ numbers up to 1023. To enable processing of >> eSPI interrupts, this patch updates the mask to 0x13FF. >> >> Signed-off-by: Leonid Komarianskyi <leonid_komarians...@epam.com> >> --- >> xen/arch/arm/include/asm/gic_v3_defs.h | 4 ++++ >> 1 file changed, 4 insertions(+) >> >> diff --git a/xen/arch/arm/include/asm/gic_v3_defs.h b/xen/arch/arm/ >> include/asm/gic_v3_defs.h >> index 7f769b38e3..2c02ddd287 100644 >> --- a/xen/arch/arm/include/asm/gic_v3_defs.h >> +++ b/xen/arch/arm/include/asm/gic_v3_defs.h >> @@ -206,7 +206,11 @@ >> #define ICH_LR_VIRTUAL_SHIFT 0 >> #define ICH_LR_CPUID_MASK 0x7 >> #define ICH_LR_CPUID_SHIFT 10 >> +#ifndef CONFIG_GICV3_ESPI >> #define ICH_LR_PHYSICAL_MASK 0x3ff >> +#else >> +#define ICH_LR_PHYSICAL_MASK 0x13ff >> +#endif > > Can't we use 0x13ff unconditionally? If not, then why is it fine to use > it on a system where GICv3 doesn't support? (I assume distros will want > to have it enabled). >> #define ICH_LR_PHYSICAL_SHIFT 32 >> #define ICH_LR_STATE_MASK 0x3 >> #define ICH_LR_STATE_SHIFT 62 > > Cheers, > You are absolutely right - we can use it unconditionally. So, I will remove the unnecessary #ifdef in v2.
Thanks for pointing that out. Cheers, Leonid
