On 25/06/2025 10:25 am, Jan Beulich wrote:
> On 24.06.2025 18:39, Andrew Cooper wrote:
>> Commit 48d32458bcd4 ("x86, idle: add barriers to CLFLUSH workaround") was
>> inherited from Linux and added MFENCEs around the AAI65 errata fix.
>>
>> The SDM now states:
>>
>> Executions of the CLFLUSH instruction are ordered with respect to each
>> other and with respect to writes, locked read-modify-write instructions,
>> and fence instructions[1].
>>
>> with footnote 1 reading:
>>
>> Earlier versions of this manual specified that executions of the CLFLUSH
>> instruction were ordered only by the MFENCE instruction. All processors
>> implementing the CLFLUSH instruction also order it relative to the other
>> operations enumerated above.
>>
>> I.e. the MFENCEs came about because of an incorrect statement in the SDM.
> And their exact placement even differed between the two sites.
>
>> The Spec Update (no longer available on Intel's website) simply says "issue a
>> CLFLUSH", with no mention of MFENCEs.
>>
>> As this erratum is specific to Intel, it's fine to remove the the MFENCEs;
>> AMD
>> CPUs of a similar vintage do port otherwise-unordered CLFLUSHs.
> Nit: DYM "sport"? I think the corresponding Linux commit that I once looked
> at has it that way.
Oops, yes I did.
>
>> Move the feature bit into the BUG range (rather than FEATURE), and move the
>> workaround into monitor() itself.
>>
>> The erratum check itself must use setup_force_cpu_cap(). It needs activating
>> if any CPU needs it, not if all of them need it.
>>
>> Fixes: 48d32458bcd4 ("x86, idle: add barriers to CLFLUSH workaround")
>> Fixes: 96d1b237ae9b ("x86/Intel: work around Xeon 7400 series erratum AAI65")
>> Link:
>> https://web.archive.org/web/20090219054841/http://download.intel.com/design/xeon/specupdt/32033601.pdf
>> Signed-off-by: Andrew Cooper <andrew.coop...@citrix.com>
> Reviewed-by: Jan Beulich <jbeul...@suse.com>
Thanks.
~Andrew
