On 08.01.2025 11:11, Jan Beulich wrote: > --- a/xen/arch/x86/cpu-policy.c > +++ b/xen/arch/x86/cpu-policy.c > @@ -487,6 +487,12 @@ static void __init guest_common_max_feat > */ > if ( test_bit(X86_FEATURE_RTM, fs) ) > __set_bit(X86_FEATURE_RTM_ALWAYS_ABORT, fs); > + > + /* > + * We expose MISC_ENABLE to guests, so our internal clearing of ERMS when > + * FAST_STRING is not set should not affect the view of migrating-in > guests. > + */ > + __set_bit(X86_FEATURE_ERMS, fs); > } > > static void __init guest_common_default_feature_adjustments(uint32_t *fs) > @@ -591,6 +597,15 @@ static void __init guest_common_feature_ > */ > if ( host_cpu_policy.feat.ibrsb ) > __set_bit(X86_FEATURE_IBPB, fs); > + > + /* > + * We expose MISC_ENABLE to guests, so our internal clearing of ERMS when > + * FAST_STRING is not set should not propagate to guest view. Guests can > + * judge on their own whether to ignore the CPUID bit when the MSR bit is > + * clear. > + */ > + if ( raw_cpu_policy.feat.erms ) > + __set_bit(X86_FEATURE_ERMS, fs); > } > > static void __init calculate_pv_max_policy(void)
While doing unrelated work in this area I noticed that this hunk is wrong, and wants to be @@ -567,6 +573,16 @@ static void __init guest_common_default_ __clear_bit(X86_FEATURE_RTM, fs); __set_bit(X86_FEATURE_RTM_ALWAYS_ABORT, fs); } + + /* + * We expose MISC_ENABLE to guests, so our internal clearing of ERMS when + * FAST_STRING is not set should not propagate to guest view. Guests can + * judge on their own whether to ignore the CPUID bit when the MSR bit is + * clear. The bit being uniformly set in the max policies, we only need + * to clear it here (if hardware doesn't have it). + */ + if ( !raw_cpu_policy.feat.erms ) + __clear_bit(X86_FEATURE_ERMS, fs); } static void __init guest_common_feature_adjustments(uint32_t *fs) instead. Fixed locally. Jan