On 3/17/25 4:46 PM, Jan Beulich wrote:
On 11.03.2025 17:19, Oleksii Kurochko wrote:
--- a/xen/arch/riscv/setup.c
+++ b/xen/arch/riscv/setup.c
@@ -16,6 +16,7 @@
#include <asm/cpufeature.h>
#include <asm/early_printk.h>
#include <asm/fixmap.h>
+#include <asm/intc.h>
#include <asm/sbi.h>
#include <asm/setup.h>
#include <asm/smp.h>
@@ -128,6 +129,8 @@ void __init noreturn start_xen(unsigned long bootcpu_id,
preinit_xen_time();
+ intc_preinit();
And there's only ever going to be a single interrupt controller type on RISC-V?
IOW - no abstraction needed?
Yes, we are going to have a single interrupt controller on RISC-V.
At least, at the moment in downstream we don't have other cases.
make_intc_node() (it is
introduced only in downstream) which is used during domain build also expects
only having one interrupt controller.
Also, Arm lives for a long time with single interrupt controller.
~ Oleksii
