Hi Luca,
On 28/02/2025 16:18, Luca Fancellu wrote:
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Provide a function that creates a pr_t object from a memory
range and some attributes.
Signed-off-by: Luca Fancellu <luca.fance...@arm.com>
---
xen/arch/arm/include/asm/arm64/mpu.h | 15 ++++++
xen/arch/arm/include/asm/mpu/mm.h | 3 ++
xen/arch/arm/mpu/mm.c | 73 ++++++++++++++++++++++++++++
3 files changed, 91 insertions(+)
diff --git a/xen/arch/arm/include/asm/arm64/mpu.h
b/xen/arch/arm/include/asm/arm64/mpu.h
index 3a09339818a0..dce77da60110 100644
--- a/xen/arch/arm/include/asm/arm64/mpu.h
+++ b/xen/arch/arm/include/asm/arm64/mpu.h
@@ -17,6 +17,21 @@
#define MAX_MPU_REGIONS NUM_MPU_REGIONS_MASK
+/* Access permission attributes. */
+/* Read/Write at EL2, No Access at EL1/EL0. */
+#define AP_RW_EL2 0x0
This is common as well between arm64 and arm32.
+
+/*
+ * Excute never.
+ * Stage 1 EL2 translation regime.
+ * XN[1] determines whether execution of the instruction fetched from the MPU
+ * memory region is permitted.
+ * Stage 2 EL1/EL0 translation regime.
+ * XN[0] determines whether execution of the instruction fetched from the MPU
+ * memory region is permitted.
+ */
+#define XN_ENABLED 0x2
This seems incorrect.
As per ARM DDI 0600A.d ID120821, G1.3.19 PRBAR<n>_EL2 (armv8 R64 supplement)
0b00 Execution of instructions fetched from the region is permitted.
0b01 Execution of instructions fetched from the region is not permitted.
This holds true for 32-bit as well (except for the fact that XN is
denoted by 1-bit).
So the correct definition is
#define XN_ENABLED 0x0
And this is common between arm32/64 , thus it can be moved to common file as
well.
+
#ifndef __ASSEMBLY__
/* Protection Region Base Address Register */
diff --git a/xen/arch/arm/include/asm/mpu/mm.h
b/xen/arch/arm/include/asm/mpu/mm.h
index 1287a0f625b5..e234f6c26193 100644
--- a/xen/arch/arm/include/asm/mpu/mm.h
+++ b/xen/arch/arm/include/asm/mpu/mm.h
@@ -44,6 +44,9 @@ extern void read_protection_region(pr_t *pr_read, uint8_t
sel);
/* Writes the MPU region with index 'sel' to the HW */
extern void write_protection_region(const pr_t *pr_write, uint8_t sel);
+/* Creates a pr_t entry for the MPU data structure */
+extern pr_t pr_of_xenaddr(paddr_t base, paddr_t limit, unsigned attr);
+
#endif /* __ARM_MPU_MM__ */
/*
diff --git a/xen/arch/arm/mpu/mm.c b/xen/arch/arm/mpu/mm.c
index bb8e0c546e7b..fb94f5d1d93d 100644
--- a/xen/arch/arm/mpu/mm.c
+++ b/xen/arch/arm/mpu/mm.c
@@ -9,6 +9,7 @@
*/
#include <asm/mpu/mm.h>
+#include <asm/page.h>
#include <asm/sysregs.h>
/* EL2 Xen MPU memory region mapping table. */
@@ -141,6 +142,78 @@ void write_protection_region(const pr_t *pr_write, uint8_t
sel)
}
}
+/*
+ * Standard entry for building up the structure of MPU memory region(pr_t).
+ * It is equivalent to mfn_to_xen_entry in MMU system.
+ * Base and limit refer to exclusive range [start, limit].
+ */
+pr_t pr_of_xenaddr(paddr_t base, paddr_t limit, unsigned attr)
+{
+ prbar_t prbar;
+ prlar_t prlar;
+ pr_t region;
+
+ /* Build up value for PRBAR_EL2. */
+ prbar = (prbar_t) {
+ .reg = {
+ .ap = AP_RW_EL2, /* Read/Write at EL2, no access at EL1/EL0. */
+ .xn = XN_ENABLED, /* No need to execute outside .text */
+ }};
+
+ switch ( attr )
+ {
+ case MT_NORMAL_NC:
+ /*
+ * ARM ARM: Overlaying the shareability attribute (DDI
+ * 0406C.b B3-1376 to 1377)
+ *
+ * A memory region with a resultant memory type attribute of normal,
+ * and a resultant cacheability attribute of Inner non-cacheable,
+ * outer non-cacheable, must have a resultant shareability attribute
+ * of outer shareable, otherwise shareability is UNPREDICTABLE.
+ *
+ * On ARMv8 sharability is ignored and explicitly treated as outer
+ * shareable for normal inner non-cacheable, outer non-cacheable.
+ */
+ prbar.reg.sh = LPAE_SH_OUTER;
+ break;
+ case MT_DEVICE_nGnRnE:
+ case MT_DEVICE_nGnRE:
+ /*
+ * Shareability is ignored for non-normal memory, Outer is as
+ * good as anything.
+ *
+ * On ARMv8 sharability is ignored and explicitly treated as outer
+ * shareable for any device memory type.
+ */
+ prbar.reg.sh = LPAE_SH_OUTER;
+ break;
+ default:
+ /* Xen mappings are SMP coherent */
+ prbar.reg.sh = LPAE_SH_INNER;
+ }
+
+ /* Build up value for PRLAR_EL2. */
+ prlar = (prlar_t) {
+ .reg = {
+ .ns = 0, /* Hyp mode is in secure world */
+ .ai = attr,
+ .en = 1, /* Region enabled */
+ }};
+
+ /* Build up MPU memory region. */
+ region = (pr_t) {
+ .prbar = prbar,
+ .prlar = prlar,
+ };
+
+ /* Set base address and limit address. */
+ pr_set_base(®ion, base);
+ pr_set_limit(®ion, limit);
+
+ return region;
+}
+
- Ayan
/*
* Local variables:
* mode: C
--
2.34.1
