On 27/02/2025 8:11 am, Jan Beulich wrote: > On 26.02.2025 18:20, Andrew Cooper wrote: >> --- a/xen/arch/riscv/include/asm/bitops.h >> +++ b/xen/arch/riscv/include/asm/bitops.h >> @@ -125,6 +125,13 @@ static inline void clear_bit(int nr, volatile void *p) >> #undef NOT >> #undef __AMO >> >> +#define arch_ffs(x) ((x) ? 1 + __builtin_ctz(x) : 0) >> +#define arch_ffsl(x) ((x) ? 1 + __builtin_ctzl(x) : 0) >> +#define arch_fls(x) ((x) ? 32 - __builtin_clz(x) : 0) > I fear you won't like me to say this, but can't we avoid baking in yet > another assumption on sizeof(int) == 4, by using at least sizeof(int) * 8 > here (yet better might be sizeof(int) * BITS_PER_BYTE)?
Yes and no. No, because 32 here is consistent with ARM and PPC when it comes to arch_fls(). Given the effort it took to get these consistent, I'm not interested in letting them diverge. But, if someone wants to introduce BITS_PER_INT to mirror BITS_PER_LONG and use it consistently, then that would be ok too. > >> +#define arch_flsl(x) ((x) ? BITS_PER_LONG - __builtin_clzl(x) : 0) >> + >> +#define arch_heightl(x) __builtin_popcountl(x) > arch_hweightl()? Oops yes. And RISC-V does have two uses, via __bitmap_weight. ~Andrew
