All the EL2 MMU specific registers in head.S are enclosed within CONFIG_MMU.
Signed-off-by: Ayan Kumar Halder <ayan.kumar.hal...@amd.com> --- xen/arch/arm/arm32/head.S | 2 ++ 1 file changed, 2 insertions(+) diff --git a/xen/arch/arm/arm32/head.S b/xen/arch/arm/arm32/head.S index 4ff5c220bc..1d0f84b18f 100644 --- a/xen/arch/arm/arm32/head.S +++ b/xen/arch/arm/arm32/head.S @@ -224,6 +224,7 @@ cpu_init_done: mcr CP32(r0, HMAIR0) mcr CP32(r1, HMAIR1) +#ifdef CONFIG_MMU /* * Set up the HTCR: * PT walks use Inner-Shareable accesses, @@ -232,6 +233,7 @@ cpu_init_done: */ mov_w r0, (TCR_RES1|TCR_SH0_IS|TCR_ORGN0_WBWA|TCR_IRGN0_WBWA|TCR_T0SZ(0)) mcr CP32(r0, HTCR) +#endif mov_w r0, HSCTLR_SET mcr CP32(r0, HSCTLR) -- 2.25.1