On 08/01/2025 9:15 am, Oleksii Kurochko wrote: > > > On 12/31/24 8:20 PM, Andrew Cooper wrote: >> AMD have always used the architectural MSRs for LER. As the first processor >> to support LER was the K7 (which was 32bit), we can assume it's presence >> unconditionally in 64bit mode. >> >> Intel are about to run out of space in Family 6 and start using 19. It is >> only the Pentium 4 which uses non-architectural LER MSRs. >> >> percpu_traps_init(), which runs on every CPU, contains a lot of code which >> should be init-only, and is the only reason why opt_ler can't be in initdata. >> >> Write a brand new init_ler() which expects all future Intel and AMD CPUs to >> continue using the architectural MSRs, and does all setup together. Call it >> from trap_init(), and remove the setup logic percpu_traps_init() except for >> the single path configuring MSR_IA32_DEBUGCTLMSR. >> >> Leave behind a warning if the user asked for LER and Xen couldn't enable it. >> >> Signed-off-by: Andrew Cooper <andrew.coop...@citrix.com> >> --- >> CC: Jan Beulich <jbeul...@suse.com> >> CC: Roger Pau Monné <roger....@citrix.com> >> CC: Oleksii Kurochko <oleksii.kuroc...@gmail.com> >> >> For 4.20. This is needed for Zen5 CPUs (already available) as well as Intel >> CPUs coming shortly. It also moves some non-init logic to being init-only. > As a user can enable/disable LER and support for Zen5/Diamond Rapids is > added, and this patch > is already in staging, I think we could mention that in CHANGELOG. If it > makes sense I can do > that during finalization of CHANGELOG before release. Does it make sense?
LER is for advanced debugging. I don't think it's user-interesting enough to justify calling out in Changelog. I am intending to do a Changelog entry for Zen5 support generally, although I'm holding out hope that AMD will publish an updated APM so I can cross check a few extra details before we get too deep into the Xen 4.20 release. ~Andrew
