On 06/01/2025 3:17 pm, Jan Beulich wrote: > On 06.01.2025 16:12, Andrew Cooper wrote: >> On 06/01/2025 2:41 pm, Jan Beulich wrote: >>> On 06.01.2025 15:19, Andrew Cooper wrote: >>>> --- a/xen/arch/x86/cpu/microcode/amd.c >>>> +++ b/xen/arch/x86/cpu/microcode/amd.c >>>> @@ -114,6 +114,7 @@ static bool verify_patch_size(uint32_t patch_size) >>>> #define F16H_MPB_MAX_SIZE 3458 >>>> #define F17H_MPB_MAX_SIZE 3200 >>>> #define F19H_MPB_MAX_SIZE 5568 >>>> +#define F1AH_MPB_MAX_SIZE 14368 >>> Yet another pretty odd number. Are these actually documented anywhere? >> In the PPRs. > So to find the number to use it's really ... > >>> And what has come of their plan to make ucode size available via CPUID >>> (for which I even sent a patch quite a long while ago)? >> This check in this function need to work for any microcode we find in >> the container. Knowing the size of the current CPU doesn't help parsing >> others. >> >> And talking of, I've just found another Fam1Ah processor with an even >> larger patch size. This limit needs bumping to 15296. > ... digging through the PPRs (and hoping no later model will have yet > larger size).
Correct. I'd prefer a better approach, but alas. ~Andrew
