> On 9 Sep 2024, at 10:14, Julien Grall <jul...@xen.org> wrote: > > > > On 09/09/2024 09:48, Luca Fancellu wrote: >> Hi Julien, Ayan, >>>>> >>>>>> + msr PRBAR_EL2, \prbar >>>>>> + msr PRLAR_EL2, \prlar >>>>>> + dsb sy >>>> This should be visible to outer shareable domain atleast. The reason being >>>> one can use the SH[1:0] bits in PRBAR_EL2 to set the region to outer >>>> shareable. >>>> Thus, the writes to these registers should be visible to outer shareable >>>> domain as well. >>> >>> I am a bit confused. SH[1:0] is about how the region will be accessed not >>> up to where should registers are visible. I was expecting that the MPU >>> registers only need to be visible to the MPU itself. >>> >>> For instance, when using the MMU, the translation unit is in the >>> non-shareable domain. So a 'nsh' is sufficient regardless of the >>> shareability of the page/block. >>> >>> This is explicitely written in the Arm Arm (see D5-4929 in ARM DDI 0487H.a) >>> but I can't find a similar section for the MPU yet. Although, I would be a >>> bit surprised if the MPU is not in the non-shareable domain... Maybe this >>> could be clarified with Arm? >> I got the feedback that DSB SY is ok here > > Thanks for asking. Does this mean that a "dsb nsh" would not be sufficient?
Unfortunately no one gave a straight answer on that, I was under the impression that nsh was sufficient, but didn’t have a confirmation. I will try to chase more in deep. > >>> >>> Anyway, for now, I am open to use 'dsb sy' with a TODO to revisit it. >>> >>>>>> + isb >>> >>> Re-quoting the spec from you previous answer: >>> >>> ``` >>> Writes to MPU registers are only guaranteed to be visible >>> following a Context synchronization event and DSB operation. >>> ``` >>> >>> So this suggests that it should be first an 'isb' and then a 'dsb'. Any >>> reason you wrote it the other way around? >> I chased this internally and it was suggested the current order, dsb >> followed by the isb: DSB ensures the completion of prior >> instructions before the next executes, and then ISB ensures subsequent >> instruction fetch observes the updated MPU state. > > I am confused. "DSB" doesn't ensure any completion of instructions. It just > ensures memory access completion. Can you clarify? Sorry, I meant memory access completion. Cheers, Luca
