SMR masking support allows deriving a mask either using a 2-cell iommu
specifier (per master) or stream-match-mask SMMU dt property (global
config). Even though the mask is stored in the fwid when adding a
device (in arm_smmu_dt_xlate_generic()), we still set it to 0 when
allocating SMEs (in arm_smmu_master_alloc_smes()). So at the end, we
always ignore the mask when programming SMRn registers. This leads to
SMMU failures. Fix it by completing the support.
A bit of history:
Linux support for SMR allocation was mainly done with:
588888a7399d ("iommu/arm-smmu: Intelligent SMR allocation")
021bb8420d44 ("iommu/arm-smmu: Wire up generic configuration support")
Taking the mask into account in arm_smmu_master_alloc_smes() was added
as part of the second commit, although quite hidden in the thicket of
other changes. We backported only the first patch with: 0435784cc75d
("xen/arm: smmuv1: Intelligent SMR allocation") but the changes to take
the mask into account were missed.
Signed-off-by: Michal Orzel <michal.or...@amd.com>
---
xen/drivers/passthrough/arm/smmu.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/xen/drivers/passthrough/arm/smmu.c
b/xen/drivers/passthrough/arm/smmu.c
index f2cee82f553a..4c8a446754cc 100644
--- a/xen/drivers/passthrough/arm/smmu.c
+++ b/xen/drivers/passthrough/arm/smmu.c
@@ -1619,19 +1619,21 @@ static int arm_smmu_master_alloc_smes(struct device
*dev)
spin_lock(&smmu->stream_map_lock);
/* Figure out a viable stream map entry allocation */
for_each_cfg_sme(cfg, i, idx, fwspec->num_ids) {
+ uint16_t mask = (fwspec->ids[i] >> SMR_MASK_SHIFT) &
SMR_MASK_MASK;
+
if (idx != INVALID_SMENDX) {
ret = -EEXIST;
goto out_err;
}
- ret = arm_smmu_find_sme(smmu, fwspec->ids[i], 0);
+ ret = arm_smmu_find_sme(smmu, fwspec->ids[i], mask);
if (ret < 0)
goto out_err;
idx = ret;
if (smrs && smmu->s2crs[idx].count == 0) {
smrs[idx].id = fwspec->ids[i];
- smrs[idx].mask = 0; /* We don't currently share SMRs */
+ smrs[idx].mask = mask;
smrs[idx].valid = true;
}
smmu->s2crs[idx].count++;
--
2.25.1
