On 2024/6/17 22:52, Jan Beulich wrote: > On 17.06.2024 11:00, Jiqian Chen wrote: >> The gsi of a passthrough device must be configured for it to be >> able to be mapped into a hvm domU. >> But When dom0 is PVH, the gsis don't get registered, it causes >> the info of apic, pin and irq not be added into irq_2_pin list, >> and the handler of irq_desc is not set, then when passthrough a >> device, setting ioapic affinity and vector will fail. >> >> To fix above problem, on Linux kernel side, a new code will >> need to call PHYSDEVOP_setup_gsi for passthrough devices to >> register gsi when dom0 is PVH. >> >> So, add PHYSDEVOP_setup_gsi into hvm_physdev_op for above >> purpose. >> >> Signed-off-by: Jiqian Chen <jiqian.c...@amd.com> >> Signed-off-by: Huang Rui <ray.hu...@amd.com> >> Signed-off-by: Jiqian Chen <jiqian.c...@amd.com> >> --- >> The code link that will call this hypercall on linux kernel side is as >> follows: >> https://lore.kernel.org/xen-devel/20240607075109.126277-3-jiqian.c...@amd.com/ > > One of my v9 comments was addressed, thanks. Repeating the other, unaddressed > one here: > "As to GSIs not being registered: If that's not a problem for Dom0's own > operation, I think it'll also want/need explaining why what is sufficient for > Dom0 alone isn't sufficient when pass-through comes into play." I have modified the commit message to describe why GSIs are not registered can cause passthrough not work, according to this v9 comment. " it causes the info of apic, pin and irq not be added into irq_2_pin list, and the handler of irq_desc is not set, then when passthrough a device, setting ioapic affinity and vector will fail." What description do you want me to add?
> > Jan > -- Best regards, Jiqian Chen.
