On 13.06.2024 18:04, Roger Pau Monné wrote:
> On Thu, Jun 13, 2024 at 05:53:02PM +0200, Jan Beulich wrote:
>> On 13.06.2024 17:16, Roger Pau Monné wrote:
>>> On Thu, Jun 13, 2024 at 10:19:30AM +0200, Jan Beulich wrote:
>>>> @@ -315,16 +329,7 @@ static void cf_check early_init_intel(st
>>>> bootsym(trampoline_misc_enable_off) &
>>>> MSR_IA32_MISC_ENABLE_XD_DISABLE)
>>>> printk(KERN_INFO "re-enabled NX (Execute Disable)
>>>> protection\n");
>>>>
>>>> - /* Unmask CPUID levels and NX if masked: */
>>>> - rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
>>>> -
>>>> - disable = misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID;
>>>> - if (disable) {
>>>> - wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable & ~disable);
>>>> - bootsym(trampoline_misc_enable_off) |= disable;
>>>> - printk(KERN_INFO "revised cpuid level: %d\n",
>>>> - cpuid_eax(0));
>>>> - }
>>>> + intel_unlock_cpuid_leaves(c);
>>>
>>> Do you really need to call intel_unlock_cpuid_leaves() here?
>>>
>>> For the BSP it will be taken care in early_cpu_init(), and for the APs
>>> MSR_IA32_MISC_ENABLE it will be set as part of the trampoline with the
>>> disables from trampoline_misc_enable_off.
>>
>> The way the original code works, it allows to deal with the BSP having the
>> bit clear, but some or all of the APs having it set. I simply didn't want
>> to break that property.
>
> Oh, I see. This looks like something we would unconditionally like to
> set in trampoline_misc_enable_off? Except that would trigger an
> unnecessary write to the MSR if the CPU already has it disabled.
Might be an option; the extra MSR access may not be _that_ harmful.
> Reviewed-by: Roger Pau Monné <roger....@citrix.com>
Thanks.
> I think the printk could be made a printk_once, since it doesn't even
> print the CPU where the bit has been seen as set, but anyway, that
> would be further adjustments.
Well, yes and no. Having it the way it is now and seeing the message twice
in a log would be indicative of a problem.
Jan
