On 29/05/2024 8:07 pm, Andrew Cooper wrote: > On 27/05/2024 7:26 am, Jan Beulich wrote: >> On 24.05.2024 22:03, Andrew Cooper wrote: >>> This is in order to maintain bisectability through the subsequent changes, >>> where flsl() changes sign-ness non-atomically by architecture. >>> >>> Signed-off-by: Andrew Cooper <andrew.coop...@citrix.com> >> Reviewed-by: Jan Beulich <jbeul...@suse.com> >> >> > Actually, by coercing the min() in pvh_populate_memory_range() from > patch 9 in this patch, the bisection-complexity of this series drops > massively, and in particular I can merge patch 3 into 10. > > As you've given R-by on both, I'm going to go ahead and do this in order > to make some headway on the series, given the deadlines, and that the > RISC-V series is still pending this one.
Actually not quite. It's even more simple. This patch stays the same, and the coercion gets added as find_first_set_bit() turns into ffsl(). ~Andrew
