This run is configured for baseline tests only. flight 74759 ovmf real [real] http://osstest.xs.citrite.net/~osstest/testlogs/logs/74759/
Perfect :-) All tests in this flight passed as required version targeted for testing: ovmf d92336541782f9d51b6a6fb743e14d5ef754deeb baseline version: ovmf 20274d2389eb012812f4561c8eb7cffc57a68850 Last test of basis 74755 2018-05-28 18:52:10 Z 1 days Testing same since 74759 2018-05-29 11:18:49 Z 0 days 1 attempts ------------------------------------------------------------ People who touched revisions under test: Marvin Haeuser <[email protected]> [email protected] <[email protected]> Ruiyu Ni <[email protected]> jobs: build-amd64-xsm pass build-i386-xsm pass build-amd64 pass build-i386 pass build-amd64-libvirt pass build-i386-libvirt pass build-amd64-pvops pass build-i386-pvops pass test-amd64-amd64-xl-qemuu-ovmf-amd64 pass test-amd64-i386-xl-qemuu-ovmf-amd64 pass ------------------------------------------------------------ sg-report-flight on osstest.xs.citrite.net logs: /home/osstest/logs images: /home/osstest/images Logs, config files, etc. are available at http://osstest.xs.citrite.net/~osstest/testlogs/logs Test harness code can be found at http://xenbits.xensource.com/gitweb?p=osstest.git;a=summary Push not applicable. ------------------------------------------------------------ commit d92336541782f9d51b6a6fb743e14d5ef754deeb Author: Ruiyu Ni <[email protected]> Date: Fri May 25 17:57:37 2018 +0800 MdeModulePkg/PciBus: Do not enable MemWriteAndInvalidate bit for PCIE Per PCIE spec, Memory Write and Invalidate is hardwired to 0b so PciBus driver shouldn't write 1b to it. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <[email protected]> Reviewed-by: Star Zeng <[email protected]> Reviewed-by: Chasel Chiu <[email protected]> commit 2b5f0daa6c5f1d205b82c52c9ce55307a1787a3e Author: Ruiyu Ni <[email protected]> Date: Fri May 25 17:47:43 2018 +0800 MdeModulePkg/PciBus: Remove unnecessary PCIE detection CreatePciIoDevice() detects whether the PCI device is a PCI Express device and remembers the device type in PciIoDevice->IsPciExp. RegisterPciDevice() detects the device type again which is unnecessary. The detection logic can be removed. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <[email protected]> Reviewed-by: Star Zeng <[email protected]> Cc: Hao A Wu <[email protected]> commit 60cb4d1b04b6334cf9d56eb95d135546053db1fd Author: Ruiyu Ni <[email protected]> Date: Fri May 25 17:00:16 2018 +0800 UefiCpuPkg/CpuCommonFeatures: Follow SDM for MAX CPUID feature detect According to IA manual: "Before setting this bit (MSR_IA32_MISC_ENABLE[22]) , BIOS must execute the CPUID.0H and examine the maximum value returned in EAX[7:0]. If the maximum value is greater than 2, this bit is supported." We need to fix our current detection logic to compare against 2. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <[email protected]> Reviewed-by: Eric Dong <[email protected]> Cc: Ming Shao <[email protected]> commit 36dd3c781e204a97d548ce3595ef6f6b6337bc1f Author: Ruiyu Ni <[email protected]> Date: Fri May 25 16:29:48 2018 +0800 PcAtChipsetPkg/PcRtc: Add two new PCD for RTC Index/Target registers In certain HW implementation, the BIT7 of RTC Index register(0x70) is for NMI sources enable/disable but the BIT7 of 0x70 cannot be read before writing. Software which doesn't want to change the NMI sources enable/disable setting can write to the alias register 0x74, through which only BIT0 ~ BIT6 of 0x70 is modified. So two new PCDs are added so that platform can have the flexibility to change the default RTC register addresses from 0x70/0x71 to 0x74/0x75. With the new PCDs added, it can also support special HW that provides RTC storage in a different register pairs. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <[email protected]> Reviewed-by: Star Zeng <[email protected]> commit 5a57246eab80f00ae2481970d12a2abc345a2730 Author: [email protected] <[email protected]> Date: Sat May 19 18:50:25 2018 +0800 BaseTools: Rename String to StringUtils. For case-insensitive file systems, edk2 String.py collides with the Python string.py, which results in build errors. This,for example, applies to building via the Windows Subsystem for Linux from a DriveFS file system. This patch renames String to StringUtils to prevent conflicts for case-insensitive file systems. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marvin Haeuser <[email protected]> Reviewed-by: Liming Gao <[email protected]> commit ba94c38f08734fa10143f44955c705ed9d14faf4 Author: [email protected] <[email protected]> Date: Thu May 17 20:41:41 2018 +0800 MdePkg: Update MmSwDispatch.h's references to SmmSw2Dispatch. MmSwDispatch.h current refers to the deprecated SmmSw2Dispatch protocol. Replace those references with the new MmSwDispatch name. V2: - Do not change the copyright date as requested. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marvin Haeuser <[email protected]> Reviewed-by: Liming Gao <[email protected]> commit c9734786da91a545bcaea16b04fbbcd3a507a8ef Author: [email protected] <[email protected]> Date: Thu May 17 20:41:38 2018 +0800 MdePkg/Hpet: Add Event Timer Block ID definition. This patch adds the HPET Event Timer Block ID definition that can be found in the IA-PC HPET Specification, section 3.2.4. V2: - Do not change the copyright date as requested. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marvin Haeuser <[email protected]> Reviewed-by: Liming Gao <[email protected]> _______________________________________________ Xen-devel mailing list [email protected] https://lists.xenproject.org/mailman/listinfo/xen-devel
