Hi Ayan,
On 21/03/2023 14:03, Ayan Kumar Halder wrote:
Refer ARM IHI 0062D.c ID070116 (SMMU 2.0 spec), 17-360, 17.3.9,
SMMU_CBn_TTBR0 is a 64 bit register. Thus, one can use
writeq_relaxed_non_atomic() to write to it instead of invoking
writel_relaxed() twice for lower half and upper half of the register.
This also helps us as p2maddr is 'paddr_t' (which may be u32 in future).
Thus, one can assign p2maddr to a 64 bit register and do the bit
manipulations on it, to generate the value for SMMU_CBn_TTBR0.
Reviewed-by: Stefano Stabellini <sstabell...@kernel.org>
Signed-off-by: Ayan Kumar Halder <ayan.kumar.hal...@amd.com>
The tags should be ordered in a timeline. So Signed-off-by should be first.
I am happy to do it on commit if you can confirm that this patch doesn't
dependent on the patches before.
Cheers,
--
Julien Grall
