On 15.02.2023 16:38, Sergey Dyasli wrote: > The original issue has been reported on AMD Bulldozer-based CPUs where > ucode loading loses the LWP feature bit in order to gain the IBPB bit. > LWP disabling is per-SMT/CMT core modification and needs to happen on > each sibling thread despite the shared microcode engine. Otherwise, > logical CPUs will end up with different cpuid capabilities. > Link: https://bugzilla.kernel.org/show_bug.cgi?id=216211 > > Guests running under Xen happen to be not affected because of levelling > logic for the feature masking/override MSRs which causes the LWP bit to > fall out and hides the issue. The latest recommendation from AMD, after > discussing this bug, is to load ucode on every logical CPU. > > In Linux kernel this issue has been addressed by e7ad18d1169c > ("x86/microcode/AMD: Apply the patch early on every logical thread"). > Follow the same approach in Xen. > > Introduce SAME_UCODE match result and use it for early AMD ucode > loading. Take this opportunity and move opt_ucode_allow_same out of > compare_revisions() to the relevant callers and also modify the warning > message based on it. Intel's side of things is modified for consistency > but provides no functional change. > > Signed-off-by: Sergey Dyasli <sergey.dya...@citrix.com>
Reviewed-by: Jan Beulich <jbeul...@suse.com>
