Hi Andrew, In the previous version of the patch series you mentioned that it is possible to re-use some parts from the existing code base.
Could you please provide me with an example? I assume that __ASM_STR should be present somewhere but other parts of the header looks like it is arch-specific. ~ Oleksii On Fri, 2023-01-27 at 15:59 +0200, Oleksii Kurochko wrote: > Signed-off-by: Oleksii Kurochko <oleksii.kuroc...@gmail.com> > --- > Changes in V2: > - Nothing changed > --- > xen/arch/riscv/include/asm/asm.h | 54 > ++++++++++++++++++++++++++++++++ > 1 file changed, 54 insertions(+) > create mode 100644 xen/arch/riscv/include/asm/asm.h > > diff --git a/xen/arch/riscv/include/asm/asm.h > b/xen/arch/riscv/include/asm/asm.h > new file mode 100644 > index 0000000000..6d426ecea7 > --- /dev/null > +++ b/xen/arch/riscv/include/asm/asm.h > @@ -0,0 +1,54 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only) */ > +/* > + * Copyright (C) 2015 Regents of the University of California > + */ > + > +#ifndef _ASM_RISCV_ASM_H > +#define _ASM_RISCV_ASM_H > + > +#ifdef __ASSEMBLY__ > +#define __ASM_STR(x) x > +#else > +#define __ASM_STR(x) #x > +#endif > + > +#if __riscv_xlen == 64 > +#define __REG_SEL(a, b) __ASM_STR(a) > +#elif __riscv_xlen == 32 > +#define __REG_SEL(a, b) __ASM_STR(b) > +#else > +#error "Unexpected __riscv_xlen" > +#endif > + > +#define REG_L __REG_SEL(ld, lw) > +#define REG_S __REG_SEL(sd, sw) > + > +#if __SIZEOF_POINTER__ == 8 > +#ifdef __ASSEMBLY__ > +#define RISCV_PTR .dword > +#else > +#define RISCV_PTR ".dword" > +#endif > +#elif __SIZEOF_POINTER__ == 4 > +#ifdef __ASSEMBLY__ > +#define RISCV_PTR .word > +#else > +#define RISCV_PTR ".word" > +#endif > +#else > +#error "Unexpected __SIZEOF_POINTER__" > +#endif > + > +#if (__SIZEOF_INT__ == 4) > +#define RISCV_INT __ASM_STR(.word) > +#else > +#error "Unexpected __SIZEOF_INT__" > +#endif > + > +#if (__SIZEOF_SHORT__ == 2) > +#define RISCV_SHORT __ASM_STR(.half) > +#else > +#error "Unexpected __SIZEOF_SHORT__" > +#endif > + > +#endif /* _ASM_RISCV_ASM_H */
