Hi Julien, > -----Original Message----- > From: Julien Grall <jul...@xen.org> > Sent: 2023年1月18日 7:17 > To: Penny Zheng <penny.zh...@arm.com>; xen-devel@lists.xenproject.org > Cc: Wei Chen <wei.c...@arm.com>; Stefano Stabellini > <sstabell...@kernel.org>; Bertrand Marquis <bertrand.marq...@arm.com>; > Volodymyr Babchuk <volodymyr_babc...@epam.com> > Subject: Re: [PATCH v2 03/40] xen/arm: adjust Xen TLB helpers for Armv8- > R64 PMSA > > Hi, > > On 13/01/2023 05:28, Penny Zheng wrote: > > From: Wei Chen <wei.c...@arm.com> > > > > From Arm ARM Supplement of Armv8-R AArch64 (DDI 0600A) [1], > > section D1.6.2 TLB maintenance instructions, we know that > > Armv8-R AArch64 permits an implementation to cache stage 1 > > VMSAv8-64 and stage 2 PMSAv8-64 attributes as a common entry > > for the Secure EL1&0 translation regime. But for Xen itself, > > it's running with stage 1 PMSAv8-64 on Armv8-R AArch64. The > > EL2 MPU updates for stage 1 PMSAv8-64 will not be cached in > > TLB entries. So we don't need any TLB invalidation for Xen > > itself in EL2. > > So I understand the theory here. But I would expect that none of the > common code will call any of those helpers. Therefore the #ifdef should > be unnecessary. > > Can you clarify if my understanding is correct? >
Yes, you're right, after we separate common code and MMU code, these helpers will be called in MMU specific code only. We will drop this patch in next version. Cheers, Wei Chen > Cheers, > > -- > Julien Grall
