Hi Julien,
> -----Original Message-----
> Subject: [PATCH v4 02/14] xen/arm64: flushtlb: Implement the TLBI repeat
> workaround for TLB flush by VA
>
> From: Julien Grall <jgr...@amazon.com>
>
> Looking at the Neoverse N1 errata document, it is not clear to me
> why the TLBI repeat workaround is not applied for TLB flush by VA.
>
> The TBL flush by VA helpers are used in flush_xen_tlb_range_va_local()
> and flush_xen_tlb_range_va(). So if the range size if a fixed size smaller
> than a PAGE_SIZE, it would be possible that the compiler remove the loop
> and therefore replicate the sequence described in the erratum 1286807.
>
> So the TLBI repeat workaround should also be applied for the TLB flush
> by VA helpers.
>
> Fixes: 22e323d115d8 ("xen/arm: Add workaround for Cortex-A76/Neoverse-
> N1 erratum #1286807")
> Signed-off-by: Julien Grall <jgr...@amazon.com>
> Reviewed-by: Michal Orzel <michal.or...@amd.com>
>
> ----
> This was spotted while looking at reducing the scope of the memory
> barriers. I don't have any HW affected.
Seeing this scissors line comment, I tried to test this patch using basically
the same approach that I did for patch#1 on every board that I can find,
including some Neoverse N1 boards, and this patch looks good, so:
Tested-by: Henry Wang <henry.w...@arm.com>
Kind regards,
Henry
