paddr_t may be u64 or u32 depending of the type of architecture.
Thus, while translating between u64 and paddr_t, one should check that the
truncated bits are 0. If not, then raise an appropriate error.
Signed-off-by: Ayan Kumar Halder <ayan.kumar.hal...@amd.com>
---
xen/arch/arm/include/asm/platform.h | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/xen/arch/arm/include/asm/platform.h
b/xen/arch/arm/include/asm/platform.h
index 997eb25216..6be1549f09 100644
--- a/xen/arch/arm/include/asm/platform.h
+++ b/xen/arch/arm/include/asm/platform.h
@@ -42,6 +42,32 @@ struct platform_desc {
unsigned int dma_bitsize;
};
+static inline int translate_dt_address_size(u64 *dt_addr, u64 *dt_size,
+ paddr_t *addr, paddr_t *size)
+{
+#ifdef CONFIG_ARM_PA_32
+ if ( dt_addr && (*dt_addr >> PADDR_SHIFT) )
+ {
+ dprintk(XENLOG_ERR, "Error in DT. Invalid address\n");
+ return -ENXIO;
+ }
+
+ if ( dt_size && (*dt_size >> PADDR_SHIFT) )
+ {
+ dprintk(XENLOG_ERR, "Error in DT. Invalid size\n");
+ return -ENXIO;
+ }
+#endif
+
+ if ( dt_addr && addr )
+ *addr = (paddr_t) (*dt_addr);
+
+ if ( dt_size && size )
+ *size = (paddr_t) (*dt_size);
+
+ return 0;
+}
+
/*
* Quirk for platforms where device tree incorrectly reports 4K GICC
* size, but actually the two GICC register ranges are placed at 64K
--
2.17.1
