Hi Julien,
On 12/12/2022 10:55, Julien Grall wrote:
>
>
> From: Julien Grall <jgr...@amazon.com>
>
> "ldr rX, =<label>" is used to load a value from the literal pool. This
> implies a memory access.
>
> This can be avoided by using the macro mov_w which encode the value in
> the immediate of two instructions.
>
> So replace all "ldr rX, =<label>" with "mov_w rX, <label>".
>
> No functional changes intended.
>
> Signed-off-by: Julien Grall <jgr...@amazon.com>
Reviewed-by: Michal Orzel <michal.or...@amd.com>
with one small change.
>
> ---
>
> Changes in v3:
> * Patch added
> ---
> xen/arch/arm/arm32/head.S | 38 +++++++++++++++++++-------------------
> 1 file changed, 19 insertions(+), 19 deletions(-)
>
> diff --git a/xen/arch/arm/arm32/head.S b/xen/arch/arm/arm32/head.S
> index a558c2a6876e..ce680be91be1 100644
> --- a/xen/arch/arm/arm32/head.S
> +++ b/xen/arch/arm/arm32/head.S
> @@ -62,7 +62,7 @@
> .endm
>
> .macro load_paddr rb, sym
> - ldr \rb, =\sym
> + mov_w \rb, \sym
> add \rb, \rb, r10
> .endm
>
> @@ -149,7 +149,7 @@ past_zImage:
> mov r8, r2 /* r8 := DTB base address */
>
> /* Find out where we are */
> - ldr r0, =start
> + mov_w r0, start
> adr r9, start /* r9 := paddr (start) */
> sub r10, r9, r0 /* r10 := phys-offset */
>
> @@ -170,7 +170,7 @@ past_zImage:
> bl enable_mmu
>
> /* We are still in the 1:1 mapping. Jump to the runtime Virtual
> Address. */
> - ldr r0, =primary_switched
> + mov_w r0, primary_switched
> mov pc, r0
> primary_switched:
> /*
> @@ -190,7 +190,7 @@ primary_switched:
> /* Setup the arguments for start_xen and jump to C world */
> mov r0, r10 /* r0 := Physical offset */
> mov r1, r8 /* r1 := paddr(FDT) */
> - ldr r2, =start_xen
> + mov_w r2, start_xen
> b launch
> ENDPROC(start)
>
> @@ -198,7 +198,7 @@ GLOBAL(init_secondary)
> cpsid aif /* Disable all interrupts */
>
> /* Find out where we are */
> - ldr r0, =start
> + mov_w r0, start
> adr r9, start /* r9 := paddr (start) */
> sub r10, r9, r0 /* r10 := phys-offset */
>
> @@ -227,7 +227,7 @@ GLOBAL(init_secondary)
>
>
> /* We are still in the 1:1 mapping. Jump to the runtime Virtual
> Address. */
> - ldr r0, =secondary_switched
> + mov_w r0, secondary_switched
> mov pc, r0
> secondary_switched:
> /*
> @@ -236,7 +236,7 @@ secondary_switched:
> *
> * XXX: This is not compliant with the Arm Arm.
> */
> - ldr r4, =init_ttbr /* VA of HTTBR value stashed by CPU 0 */
> + mov_w r4, init_ttbr /* VA of HTTBR value stashed by CPU 0 */
> ldrd r4, r5, [r4] /* Actual value */
> dsb
> mcrr CP64(r4, r5, HTTBR)
> @@ -254,7 +254,7 @@ secondary_switched:
> #endif
> PRINT("- Ready -\r\n")
> /* Jump to C world */
> - ldr r2, =start_secondary
> + mov_w r2, start_secondary
> b launch
> ENDPROC(init_secondary)
>
> @@ -297,8 +297,8 @@ ENDPROC(check_cpu_mode)
> */
> zero_bss:
> PRINT("- Zero BSS -\r\n")
> - ldr r0, =__bss_start /* r0 := vaddr(__bss_start) */
> - ldr r1, =__bss_end /* r1 := vaddr(__bss_start) */
> + mov_w r0, __bss_start /* r0 := vaddr(__bss_start) */
> + mov_w r1, __bss_end /* r1 := vaddr(__bss_start) */
>
> mov r2, #0
> 1: str r2, [r0], #4
> @@ -330,8 +330,8 @@ cpu_init:
>
> cpu_init_done:
> /* Set up memory attribute type tables */
> - ldr r0, =MAIR0VAL
> - ldr r1, =MAIR1VAL
> + mov_w r0, MAIR0VAL
> + mov_w r1,MAIR1VAL
NIT: please separate arguments with a single space just like you did in every
other place
~Michal
