Hi Ayan,
> On 4 Nov 2022, at 16:23, Ayan Kumar Halder <ayan.kumar.hal...@amd.com> wrote:
>
> From: Ayan Kumar Halder <ayank...@amd.com>
>
> Refer ARM DDI 0487I.a ID081822, B2.2.1
> "Requirements for single-copy atomicity
>
> - A read that is generated by a load instruction that loads a single
> general-purpose register and is aligned to the size of the read in the
> instruction is single-copy atomic.
>
> -A write that is generated by a store instruction that stores a single
> general-purpose register and is aligned to the size of the write in the
> instruction is single-copy atomic"
>
> On AArch32, the alignment check is enabled at boot time by setting HSCTLR.A
> bit.
> ("HSCTLR, Hyp System Control Register").
> However in AArch64, alignment check is not enabled at boot time.
>
> Thus, one needs to check for alignment when performing atomic operations.
>
> Signed-off-by: Ayan Kumar Halder <ayan.kumar.hal...@amd.com>
> Reviewed-by: Michal Orzel <michal.or...@amd.com
Seems like the R-B is missing a >
With that fixed (can be done on commit):
Reviewed-by: Bertrand Marquis <bertrand.marq...@arm.com>
Cheers
Bertrand
> ---
>
> Changes from :-
> v1 - 1. Referred to the latest Arm Architecture Reference Manual in the commit
> message.
>
> xen/arch/arm/include/asm/atomic.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/xen/arch/arm/include/asm/atomic.h
> b/xen/arch/arm/include/asm/atomic.h
> index 1f60c28b1b..64314d59b3 100644
> --- a/xen/arch/arm/include/asm/atomic.h
> +++ b/xen/arch/arm/include/asm/atomic.h
> @@ -78,6 +78,7 @@ static always_inline void read_atomic_size(const volatile
> void *p,
> void *res,
> unsigned int size)
> {
> + ASSERT(IS_ALIGNED((vaddr_t)p, size));
> switch ( size )
> {
> case 1:
> @@ -102,6 +103,7 @@ static always_inline void write_atomic_size(volatile void
> *p,
> void *val,
> unsigned int size)
> {
> + ASSERT(IS_ALIGNED((vaddr_t)p, size));
> switch ( size )
> {
> case 1:
> --
> 2.17.1
>
