On 04/24/2018 02:51 PM, Andrew Cooper wrote:
> By default, the SYSCALL MSRs are not intercepted, and accesses are completed
> by hardware. The SYSENTER MSRs are intercepted for cross-vendor
> purposes (albeit needlessly in the common case), and are fully emulated.
>
> However, {RD,WR}MSR instructions which happen to be emulated (FEP,
> introspection, or older versions of Xen which intercepted #UD), or when the
> MSRs are explicitly intercepted (introspection), will be completed
> incorrectly.
>
> svm_msr_read_intercept() appears to return the correct values, but only
> because of the default read-everything case (which is going to disappear), and
> that in vcpu context, hardware should have the guest values in context.
> Update the read path to explicitly sync the VMCB and complete the accesses,
> rather than falling all the way through to the default case.
>
> svm_msr_write_intercept() silently discard all updates. Synchronise the VMCB
> for all applicable MSRs, and implement suitable checks. The actual behaviour
> of AMD hardware is to truncate the SYSENTER and SFMASK MSRs at 32 bits, but
> this isn't implemented yet to remain compatible with the cross-vendor case.
>
> Drop one bit of trailing whitespace while modifing this area of the code.
>
> Signed-off-by: Andrew Cooper <andrew.coop...@citrix.com>
> ---
> CC: Jan Beulich <jbeul...@suse.com>
> CC: Juergen Gross <jgr...@suse.com>
> CC: Boris Ostrovsky <boris.ostrov...@oracle.com>
> CC: Suravee Suthikulpanit <suravee.suthikulpa...@amd.com>
> CC: Brian Woods <brian.wo...@amd.com>
Reviewed-by: Boris Ostrovsky <boris.ostrov...@oracle.com>
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