From: Artem Bityutskiy <artem.bityuts...@linux.intel.com>
Add a Sapphire Rapids Xeon C6 optimization, similar to what we have for Sky Lake
Xeon: if package C6 is disabled, adjust C6 exit latency and target residency to
match core C6 values, instead of using the default package C6 values.
Signed-off-by: Artem Bityutskiy <artem.bityuts...@linux.intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wyso...@intel.com>
Origin: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
3a9cf77b60dc
Make sure a contradictory "preferred-cstates" wouldn't cause bypassing
of the added logic.
Signed-off-by: Jan Beulich <jbeul...@suse.com>
Acked-by: Roger Pau Monné <roger....@citrix.com>
---
v3: Add parentheses.
v2: Sync with the Linux side fix to the noticed issue. Re-base over
change to earlier patch.
--- a/xen/arch/x86/cpu/mwait-idle.c
+++ b/xen/arch/x86/cpu/mwait-idle.c
@@ -1273,18 +1273,31 @@ static void __init skx_idle_state_table_
*/
static void __init spr_idle_state_table_update(void)
{
- /* Check if user prefers C1E over C1. */
- if (preferred_states_mask & BIT(2, U)) {
- if (preferred_states_mask & BIT(1, U))
- /* Both can't be enabled, stick to the defaults. */
- return;
+ uint64_t msr;
+ /* Check if user prefers C1E over C1. */
+ if ((preferred_states_mask & BIT(2, U)) &&
+ !(preferred_states_mask & BIT(1, U))) {
+ /* Disable C1 and enable C1E. */
spr_cstates[0].flags |= CPUIDLE_FLAG_DISABLED;
spr_cstates[1].flags &= ~CPUIDLE_FLAG_DISABLED;
/* Request enabling C1E using the "C1E promotion" bit. */
idle_cpu_spr.c1e_promotion = C1E_PROMOTION_ENABLE;
}
+
+ /*
+ * By default, the C6 state assumes the worst-case scenario of package
+ * C6. However, if PC6 is disabled, we update the numbers to match
+ * core C6.
+ */
+ rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr);
+
+ /* Limit value 2 and above allow for PC6. */
+ if ((msr & 0x7) < 2) {
+ spr_cstates[2].exit_latency = 190;
+ spr_cstates[2].target_residency = 600;
+ }
}
/*
