On Wed, Jun 29, 2022 at 07:45:08PM +0100, Andrew Cooper wrote: > STIBP and PSFD are slightly weird bits, because they're both implied by other > bits in MSR_SPEC_CTRL. Add fine grain controls for them, and take the > implications into account when setting IBRS/SSBD. > > Rearrange the IBPB text/variables/logic to keep all the MSR_SPEC_CTRL bits > together, for consistency. > > However, AMD have a hardware hint CPUID bit recommending that STIBP be set > unilaterally. This is advertised on Zen3, so follow the recommendation. > Furthermore, in such cases, set STIBP behind the guest's back for now. This > has negligible overhead for the guest, but saves a WRMSR on vmentry. This is > the only default change. > > Signed-off-by: Andrew Cooper <andrew.coop...@citrix.com> > Reviewed-by: Jan Beulich <jbeul...@suse.com>
Reviewed-by: Roger Pau Monné <roger....@citrix.com> Thanks, Roger.
