On Wed, May 18, 2022 at 12:44:06PM +0200, Jan Beulich wrote: > On 11.05.2022 13:08, Roger Pau Monné wrote: > > On Mon, Apr 25, 2022 at 10:43:45AM +0200, Jan Beulich wrote: > >> When a page table ends up with all contiguous entries (including all > >> identical attributes), it can be replaced by a superpage entry at the > >> next higher level. The page table itself can then be scheduled for > >> freeing. > >> > >> The adjustment to LEVEL_MASK is merely to avoid leaving a latent trap > >> for whenever we (and obviously hardware) start supporting 512G mappings. > >> > >> Signed-off-by: Jan Beulich <jbeul...@suse.com> > >> Reviewed-by: Kevin Tian <kevin.t...@intel.com> > > > > Like on the AMD side, I wonder whether you can get away with only > > FTAOD I take it you mean "like on the all-empty side", as on AMD we > don't need to do any cache flushing?
Heh, yes, sorry. > > doing a cache flush for the last (highest level) PTE, as the lower > > ones won't be reachable anyway, as the page-table is freed. > > But that freeing will happen only later, with a TLB flush in between. > Until then we would better make sure the IOMMU sees what was written, > even if it reading a stale value _should_ be benign. Hm, but when doing the TLB flush the paging structures will already be fully updated, and the top level visible entry will have it's cache flushed, so the lower ones would never be reachable AFAICT. Thanks, Roger.
