After reset, IBRS is disabled by processor, but a coming intr/nmi leave IBRS
enabled after their exit. It's not necessory for bootup code to run in low
performance with IBRS enabled.
On ORACLE X6-2(500GB/88 cpus, dom0 11GB/20 vcpus), we observed an 200s+ delay
in construct_dom0.
By initializing use_shadow_spec_ctrl with 1, IBRS is disabled in intr/nmi exit
path at bootup stage. Then delay in construct_dom0 is ~50s.
Signed-off-by: Zhenzhong Duan <zhenzhong.d...@oracle.com>
---
xen/include/asm-x86/spec_ctrl.h | 3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/xen/include/asm-x86/spec_ctrl.h b/xen/include/asm-x86/spec_ctrl.h
index 5ab4ff3..c619a80 100644
--- a/xen/include/asm-x86/spec_ctrl.h
+++ b/xen/include/asm-x86/spec_ctrl.h
@@ -33,7 +33,8 @@ static inline void init_shadow_spec_ctrl_state(void)
{
struct cpu_info *info = get_cpu_info();
- info->shadow_spec_ctrl = info->use_shadow_spec_ctrl = 0;
+ info->shadow_spec_ctrl = 0;
+ info->use_shadow_spec_ctrl = 1;
info->bti_ist_info = default_bti_ist_info;
}
--
1.7.3
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