On 03/14/2018 06:09 PM, Andre Przywara wrote:
On 09/03/18 16:35, julien.gr...@arm.com wrote:
diff --git a/xen/include/asm-arm/gic_v3_defs.h
b/xen/include/asm-arm/gic_v3_defs.h
index ccb72cf0f1..817bb0d5c7 100644
--- a/xen/include/asm-arm/gic_v3_defs.h
+++ b/xen/include/asm-arm/gic_v3_defs.h
@@ -171,6 +171,8 @@
#define ICH_LR_PHYSICAL_SHIFT 32
#define ICH_LR_STATE_MASK 0x3
#define ICH_LR_STATE_SHIFT 62
+#define ICH_LR_STATE_PENDING (1UL << 62)
+#define ICH_LR_STATE_ACTIVE (1UL << 63)
Should that be 1ULL, just in case we ever get 32-bit support for GICv3?
Yes, good point. I will fix that.
Regardless of that:
Reviewed-by: Andre Przywara <andre.przyw...@arm.com>
Cheers,
--
Julien Grall
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