Hi Andre,
On 05/03/18 16:04, Andre Przywara wrote:
As this register is v2 specific, its implementation lives entirely
in vgic-mmio-v2.c.
This register allows setting the source mask of an IPI.
This is based on Linux commit ed40213ef9b0, written by Andre Przywara.
Signed-off-by: Andre Przywara <andre.przyw...@linaro.org>
Reviewed-by: Julien Grall <julien.gr...@arm.com>
Cheers,
---
Changelog RFC ... v1:
- use C99 and unsigned data types
xen/arch/arm/vgic/vgic-mmio-v2.c | 81 +++++++++++++++++++++++++++++++++++++++-
1 file changed, 79 insertions(+), 2 deletions(-)
diff --git a/xen/arch/arm/vgic/vgic-mmio-v2.c b/xen/arch/arm/vgic/vgic-mmio-v2.c
index 5f1fdb9a70..dd9857e8a6 100644
--- a/xen/arch/arm/vgic/vgic-mmio-v2.c
+++ b/xen/arch/arm/vgic/vgic-mmio-v2.c
@@ -177,6 +177,83 @@ static void vgic_mmio_write_target(struct vcpu *vcpu,
}
}
+static unsigned long vgic_mmio_read_sgipend(struct vcpu *vcpu,
+ paddr_t addr, unsigned int len)
+{
+ uint32_t intid = VGIC_ADDR_TO_INTID(addr, 8);
+ uint32_t val = 0;
+ unsigned int i;
+
+ ASSERT(intid < VGIC_NR_SGIS);
+
+ for ( i = 0; i < len; i++ )
+ {
+ struct vgic_irq *irq = vgic_get_irq(vcpu->domain, vcpu, intid + i);
+
+ val |= (uint32_t)irq->source << (i * 8);
+
+ vgic_put_irq(vcpu->domain, irq);
+ }
+
+ return val;
+}
+
+static void vgic_mmio_write_sgipendc(struct vcpu *vcpu,
+ paddr_t addr, unsigned int len,
+ unsigned long val)
+{
+ uint32_t intid = VGIC_ADDR_TO_INTID(addr, 8);
+ unsigned int i;
+ unsigned long flags;
+
+ ASSERT(intid < VGIC_NR_SGIS);
+
+ for ( i = 0; i < len; i++ )
+ {
+ struct vgic_irq *irq = vgic_get_irq(vcpu->domain, vcpu, intid + i);
+
+ spin_lock_irqsave(&irq->irq_lock, flags);
+
+ irq->source &= ~((val >> (i * 8)) & 0xff);
+ if ( !irq->source )
+ irq->pending_latch = false;
+
+ spin_unlock_irqrestore(&irq->irq_lock, flags);
+ vgic_put_irq(vcpu->domain, irq);
+ }
+}
+
+static void vgic_mmio_write_sgipends(struct vcpu *vcpu,
+ paddr_t addr, unsigned int len,
+ unsigned long val)
+{
+ uint32_t intid = VGIC_ADDR_TO_INTID(addr, 8);
+ unsigned int i;
+ unsigned long flags;
+
+ ASSERT(intid < VGIC_NR_SGIS);
+
+ for ( i = 0; i < len; i++ )
+ {
+ struct vgic_irq *irq = vgic_get_irq(vcpu->domain, vcpu, intid + i);
+
+ spin_lock_irqsave(&irq->irq_lock, flags);
+
+ irq->source |= (val >> (i * 8)) & 0xff;
+
+ if ( irq->source )
+ {
+ irq->pending_latch = true;
+ vgic_queue_irq_unlock(vcpu->domain, irq, flags);
+ }
+ else
+ {
+ spin_unlock_irqrestore(&irq->irq_lock, flags);
+ }
+ vgic_put_irq(vcpu->domain, irq);
+ }
+}
+
static const struct vgic_register_region vgic_v2_dist_registers[] = {
REGISTER_DESC_WITH_LENGTH(GICD_CTLR,
vgic_mmio_read_v2_misc, vgic_mmio_write_v2_misc, 12,
@@ -215,10 +292,10 @@ static const struct vgic_register_region
vgic_v2_dist_registers[] = {
vgic_mmio_read_raz, vgic_mmio_write_sgir, 4,
VGIC_ACCESS_32bit),
REGISTER_DESC_WITH_LENGTH(GICD_CPENDSGIR,
- vgic_mmio_read_raz, vgic_mmio_write_wi, 16,
+ vgic_mmio_read_sgipend, vgic_mmio_write_sgipendc, 16,
VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
REGISTER_DESC_WITH_LENGTH(GICD_SPENDSGIR,
- vgic_mmio_read_raz, vgic_mmio_write_wi, 16,
+ vgic_mmio_read_sgipend, vgic_mmio_write_sgipends, 16,
VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
};
--
Julien Grall
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