Hello,
On 08/03/18 06:15, Peng Fan wrote:
Hi Stefano,
On Fri, Mar 02, 2018 at 11:05:54AM -0800, Stefano Stabellini wrote:
Hi all,
This series changes the initialization of two virtual registers to make
sure they match the value of the underlying physical cpu.
It also disables cpus different from the boot cpu, unless a newly
introduced command line option is specified. In that case, it explains
how to setup the system to avoid corruptions, which involves manually
specifying the cpu affinity of all domains, because the scheduler still
lacks big.LITTLE support.
In the uncommon case of a system where the cacheline sizes are different
across cores, it disables all cores that have a different dcache line size
from the boot cpu. In fact, it is not sufficient to use the dcache line
size of the current cpu, it would be necessary to use the minimum across
all dcache line sizes of all cores. Given that it is actually uncommon
even in big.LITTLE systems, just disable cpus for now.
The first patch in the series is a fix for the way we read the dcache
line size.
I am trying the patchset, but I meet issue that Guest Big/Little with
vcpu not working properly. As my current hardware has an issue
which has fix in Kernel,
https://source.codeaurora.org/external/imx/linux-imx/commit/?h=imx_4.9.51_imx8_beta2&id=917cc3a8db2f3609ef8e2f59e7bcd31aa2cd4e59
Can you describe what you mean by not working properly? Also what is
your setup? Did you pin the different vCPUs as requested by the
documentation.
I am not sure whether this issue cause DomU big/Little not work.
Well, I would recommend to speak with NXP whether this errata affects
TLB flush for Hypervisor Page-Table or Stage-2 Page-Table.
So wonder has this patchset been tested on Big/Little Hardware?
This series only adds facility to report the correct MIDR to the guest.
If your platform requires more, then it would be necessary send a patch
for Xen.
Cheers,
--
Julien Grall
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