Hi Andre, On 05/03/18 16:03, Andre Przywara wrote:
A GICv3 hardware implementation can be implemented in several parts that communicate with each other (think multi-socket systems). To make sure that critical settings have arrived at all endpoints, some bits are tracked using the RWP bit in the GICD_CTLR register, which signals whether a register write is still in progress. However this only applies to *some* registers, namely the bits in the GICD_ICENABLER (disabling interrupts) and some bits in the GICD_CTLR register (cf. Arm IHI 0069D, 8.9.4: RWP, bit[31]). But our gicv3_poke_irq() was always polling this bit before returning, resulting in pointless MMIO reads for many registers. Add an option to gicv3_poke_irq() to state whether we want to wait for this bit and use it accordingly to match the spec.Signed-off-by: Andre Przywara <andre.przyw...@linaro.org> --- Changelog RFC ... v1: - new patch xen/arch/arm/gic-v3.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index 3e381d031b..44dfba2267 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -428,9 +428,9 @@ static void gicv3_dump_state(const struct vcpu *v) } }-static void gicv3_poke_irq(struct irq_desc *irqd, u32 offset)+static void gicv3_poke_irq(struct irq_desc *irqd, u32 offset, bool wait_for_rwp) { - u32 mask = 1 << (irqd->irq % 32); + u32 mask = 1U << (irqd->irq % 32);
Do you mind adding a word about 1U in the commit message? With that: Reviewed-by: Julien Grall <julien.gr...@arm.com> Cheers, -- Julien Grall _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel
