On 02/28/2018 10:38 AM, Razvan Cojocaru wrote: > In hardware, when PCID support is enabled and the NOFLUSH bit is set > when writing a CR3 value, the hardware will clear that that bit and > change the CR3 without flushing the TLB. hvm_set_cr3(), however, was > ignoring this bit; the result was that post-vm_event checks detected > an invalid CR3 value and crashed the domain. > > Handle NOFLUSH in hvm_set_cr3() by: > 1. Clearing the bit > 2. Passing a "noflush" flag to lower-level cr3 setting functions to > indicate that a flush should not be performed. > > Also clear X86_CR3_NOFLUSH when reporting CR3 monitored CR3 writes. > > This allows introspection to be used on VMs whose operating system uses > the NOFLUSH bit. > > Signed-off-by: Razvan Cojocaru <rcojoc...@bitdefender.com> > Reported-by: Bitweasil <bitwea...@cryptohaze.com> > Suggested-by: Andrew Cooper <andrew.coop...@citrix.com> > Acked-by: Tamas K Lengyel <ta...@tklengyel.com> > Reviewed-by: Jan Beulich <jbeul...@suse.com> > Reviewed-by: Kevin Tian <kevin.t...@intel.com> > Acked-by: George Dunlap <george.dun...@citrix.com>
Boris / Suvaree, any opinions on the SVM changes? -George _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel
