(Moving that to xen-devel + Stefano)
On 16/02/18 09:23, Iain Hunter wrote:
Hi Julian,
Hi,
The patch I applied is below. I have no idea if it is AM572x/DRA7xx
specific or just specific to the 2017.01 u-boot I was using.
Thank you for sending the patch. Indeed we don't know the state of the
TLBs when turning the MMU on. So, it is necessary to flush the TLBs.
On a side note, it looks like the Arm64 side has the same issue.
Can you submit the patch to xen-devel with a commit message and CC
Stefano and I?
From 36e6bc81803a002637c9b854f2694bc655679e85 Mon Sep 17 00:00:00 2001
From: Iain Hunter <i...@hunterembedded.co.uk
<mailto:i...@hunterembedded.co.uk>>
Date: Thu, 1 Feb 2018 14:45:27 +0000
Subject: [PATCH] for AM572x need to flush TLBs before enabling MMU
---
xen/arch/arm/arm32/head.S | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/xen/arch/arm/arm32/head.S b/xen/arch/arm/arm32/head.S
index 2df9a98..b153eeb 100644
--- a/xen/arch/arm/arm32/head.S
+++ b/xen/arch/arm/arm32/head.S
@@ -347,6 +347,17 @@ virtphys_clash:
b fail
1:
+ /*
+ * Flush the TLB before enabling MMU
+ */
+ dsb /* Ensure any page table updates
made above
+ * have occurred. */
+ isb
The dsb/isb here is not necessary. As you have MMU disabled, the TLBs
will not get speculated.
+ mov r0, #1
+ mcr CP32(r0, TLBIALLH) /* Flush hypervisor TLB */
+ dsb /* Ensure completion of TLB flush */
You want to use dsb nsh here.
+ isb
This is not necessary, you can rely on the ISB after enabling the MMU.
Cheers,
--
Julien Grall
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