Hi Jan,
On 12/11/2017 10:06 AM, Jan Beulich wrote:
On 08.12.17 at 15:38, <julien.gr...@linaro.org> wrote:
On 08/12/17 08:03, Tim Deegan wrote:
It should be possible to do something like the misconfigured-entry bit
trick by _allocating_ the memory up-front and building the p2m entries
but only making them usable by the {IO}MMUs on first access. That
would make these early p2m walks shorter (because they can skip whole
subtrees that aren't marked present yet) without making major changes
to domain build or introducing run-time failures.
I am not aware of any way on Arm to misconfigure an entry. We do have
valid and access bits, although they will affect the IOMMU as well. So
it will not be possible to get page-table sharing with this "feature"
enabled.
How would you intend to solve the IOMMU part of the problem with
PoD? As was pointed out before - IOMMU and PoD are incompatible
on x86.
I am not sure why you ask about PoD here when I acknowledge I will look
at a different solution. And again, misconfiguring an entry is not
possible on Arm.
But to answer your question, IOMMU will neither be supported with PoD
nor access/valid bit solution. And that's fine because S/W are not
easily virtualizable, I take that as a hint for "All the features may
not be available when using S/W in a guest".
Cheers,
--
Julien Grall
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