This includes support for AVX counterparts of them as well as a few
later SSE additions (basically covering the entire 0f-prefixed opcode
space, but not the 0f38 and 0f3a ones, nor 3dnow).
1: support most memory accessing MMX/SSE{,2,3} insns
2: support MMX/SSE{,2,3} moves
3: support MMX/SSE/SSE2 converts
4: support {,V}{,U}COMIS{S,D}
5: support MMX/SSE{,2,4a} insns with only register operands
6: support {,V}{LD,ST}MXCSR
7: support {,V}MOVNTDQA
8: test coverage for SSE/SSE2 insns
9: honor MMXEXT feature flag
10: add tables for 0f38 and 0f3a extension space
11: support SSSE3 insns
12: support SSE4.1 insns
13: support SSE4.2 insns
14: test coverage for SSE3/SSSE3/SSE4* insns
Partly RFC from here on, as there's testing code still mostly missing,
albeit I'm unsure whether it makes sense to cover each and every
individual instruction.
15: support PCLMULQDQ
16: support AESNI insns
17: support SHA insns
Signed-off-by: Jan Beulich <jbeul...@suse.com>
---
v4: New patch 14. Fixes to other patches see there.
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