On Intel CPU, an attemp to write to MSR_IA32_MCG_STATUS with any non-zero value would result in #GP.
This commit writes 0 on AMD CPU as well instead of just clearing MCIP bit, because all non-reserved bits of MSR_IA32_MCG_STATUS have been handled at this point. Signed-off-by: Haozhong Zhang <[email protected]> Reviewed-by: Jan Beulich <[email protected]> Reviewed-by: Boris Ostrovsky <[email protected]> --- Cc: Christoph Egger <[email protected]> Cc: Jan Beulich <[email protected]> Cc: Andrew Cooper <[email protected]> Cc: Boris Ostrovsky <[email protected]> --- xen/arch/x86/cpu/mcheck/mce.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/arch/x86/cpu/mcheck/mce.c b/xen/arch/x86/cpu/mcheck/mce.c index 53ca29c..5a7e2ba 100644 --- a/xen/arch/x86/cpu/mcheck/mce.c +++ b/xen/arch/x86/cpu/mcheck/mce.c @@ -539,7 +539,7 @@ void mcheck_cmn_handler(const struct cpu_user_regs *regs) gstatus = mca_rdmsr(MSR_IA32_MCG_STATUS); if ((gstatus & MCG_STATUS_MCIP) != 0) { mce_printk(MCE_CRITICAL, "MCE: Clear MCIP@ last step"); - mca_wrmsr(MSR_IA32_MCG_STATUS, gstatus & ~MCG_STATUS_MCIP); + mca_wrmsr(MSR_IA32_MCG_STATUS, 0); } mce_barrier_exit(&mce_trap_bar); -- 2.10.1 _______________________________________________ Xen-devel mailing list [email protected] https://lists.xen.org/xen-devel
