An attemp to write to MSR_IA32_MCG_STATUS with any value other than 0
would result in #GP on Intel CPU.
Signed-off-by: Haozhong Zhang <haozhong.zh...@intel.com>
---
Cc: Christoph Egger <cheg...@amazon.de>
Cc: Liu Jinsong <jinsong....@alibaba-inc.com>
Cc: Jan Beulich <jbeul...@suse.com>
Cc: Andrew Cooper <andrew.coop...@citrix.com>
---
xen/arch/x86/cpu/mcheck/mce.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/xen/arch/x86/cpu/mcheck/mce.c b/xen/arch/x86/cpu/mcheck/mce.c
index 28bf579..95a9da3 100644
--- a/xen/arch/x86/cpu/mcheck/mce.c
+++ b/xen/arch/x86/cpu/mcheck/mce.c
@@ -538,7 +538,14 @@ void mcheck_cmn_handler(const struct cpu_user_regs *regs)
gstatus = mca_rdmsr(MSR_IA32_MCG_STATUS);
if ((gstatus & MCG_STATUS_MCIP) != 0) {
mce_printk(MCE_CRITICAL, "MCE: Clear MCIP@ last step");
- mca_wrmsr(MSR_IA32_MCG_STATUS, gstatus & ~MCG_STATUS_MCIP);
+ if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL )
+ /*
+ * Intel SDM 3: An attempt to write to IA32_MCG_STATUS
+ * with any value other than 0 would result in #GP.
+ */
+ mca_wrmsr(MSR_IA32_MCG_STATUS, 0);
+ else
+ mca_wrmsr(MSR_IA32_MCG_STATUS, gstatus & ~MCG_STATUS_MCIP);
}
mce_barrier_exit(&mce_trap_bar);
--
2.10.1
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