On Wed, 2017-01-25 at 07:21 -0700, Jan Beulich wrote: > > Well, in the context of this XSA we've asked both of them, and iirc > we've got a vague reply from Intel and none from AMD. In fact we > did defer the XSA for quite a bit waiting for any useful feedback. > To AMD's advantage I'd like to add though that iirc they're a little > more clear in their PM about the specific question of UC and WC > you raise: They group the various cacheabilities into two groups > (cacheable and uncacheable) and require there to only not be > any mixture between groups. Iirc Intel's somewhat vague reply > allowed us to conclude we're likely safe that way on their side too.
It would be good to get a definitive answer from Intel, to match AMD's. That's basically why I added hpa to CC, in fact. Peter, is there any possibility of a clarification here, please? Thanks.
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