On 01/09/16 12:31, Andrew Cooper wrote: > On 29/08/16 14:57, Jan Beulich wrote: >> - There's no 32-bit displacement in 16-bit addressing mode. >> - It is wrong to ASSERT() anything on parts of an instruction fetched >> from guest memory. >> - The two scaling bits of a SIB byte don't affect whether there is no >> scaled index register.
"whether there is a scaled index register or not." >> >> Signed-off-by: Jan Beulich <jbeul...@suse.com> >> >> --- a/xen/arch/x86/traps.c >> +++ b/xen/arch/x86/traps.c >> @@ -3214,7 +3214,7 @@ static void emulate_gate_op(struct cpu_u >> sib = insn_fetch(u8, base, eip, limit); >> >> modrm = (modrm & ~7) | (sib & 7); >> - if ( (sib >>= 3) != 4 ) >> + if ( ((sib >>= 3) & 7) != 4 ) >> opnd_off = *(unsigned long *) >> decode_register(sib & 7, regs, 0); >> opnd_off <<= sib >> 3; > Surely should shift sib by 6 rather than 3 here, so opnd_off doesn't > have the index included in its scaling factor? Oh wait no - the if condition has a destructive shift of sib already, so this calculation is correct. (Wow I hate trying to read this code.) With the commit message tweak, Reviewed-by: Andrew Cooper <andrew.coop...@citrix.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xen.org https://lists.xen.org/xen-devel
