On Thu, Jul 28, 2016 at 11:54:27AM +0100, Andrew Cooper wrote: > On 28/07/16 11:43, George Dunlap wrote: > > On Thu, Jul 28, 2016 at 11:18 AM, Anthony PERARD > > <anthony.per...@citrix.com> wrote: > >> On Wed, Jul 27, 2016 at 03:45:23PM -0400, Boris Ostrovsky wrote: > >>> On 07/27/2016 07:35 AM, Anthony PERARD wrote: > >>>> On Wed, Jul 27, 2016 at 12:08:04PM +0100, Anthony PERARD wrote: > >>>>> I can try to describe how OVMF is setting up the memory. > >>>> From the start of the day: > >>>> setup gdt > >>>> cr0 = 0x40000023 > >>> I think this is slightly odd, with bit 30 (cache disable) set. I'd > >>> suspect that this would affect both Intel and AMD though. > >>> > >>> Can you try clearing this bit? > >> That works... > >> > >> I wonder why it does not appear to affect Intel or KVM. > > Are those bits hard-coded, or are they set based on the hardware > > that's available? > > > > Is it possible that the particular combination of CPUID bits presented > > by Xen on AMD are causing a different value to be written? > > > > Or is it possible that the cache disable bit is being ignored (by Xen) > > on Intel and KVM? > > If a guest has no hardware, then it has no reason to actually disable > caches. We should have logic to catch this an avoid actually disabling > caches when the guest asks for it.
For KVM/QEMU, the OVMF binary is loaded in a 'CFI parallel flash', which is map via mmio, so it is executed from a device memory. The memory region is marked as rom_device. -- Anthony PERARD _______________________________________________ Xen-devel mailing list Xen-devel@lists.xen.org https://lists.xen.org/xen-devel
