Hello,
On 07/06/16 17:06, Julien Grall wrote:
The ARM erratum applies to certain revisions of Cortex-A57. The
processor may report a Stage 2 translation fault as the result of
Stage 1 fault for load crossing a page boundary when there is a
permission fault or device memory fault at stage 1 and a translation
fault at Stage 2.
So Xen needs to check that Stage 1 translation does not generate a fault
before handling the Stage 2 fault. If it is a Stage 1 translation fault,
return to the guest to let the processor injecting the correct fault.
Only document it as this is already the behavior of the fault handlers.
Note that some optimization could be done to avoid unnecessary translation
fault. This is because HPFAR_EL2 is valid for more use case. For the moment,
the code is left unmodified.
Signed-off-by: Julien Grall <julien.gr...@arm.com>
Actually I am working on a patch series to optimize the data handles
(i.e to avoid unnecessary translation). I don't think the documentation
is strictly necessary for now. So I will drop this patch and implement
the workaround on top of the other series.
Regards,
--
Julien Grall
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