On Fri, Jun 3, 2016 at 4:34 AM, Jan Beulich <jbeul...@suse.com> wrote:
>>>> On 03.06.16 at 00:52, <ta...@tklengyel.com> wrote:
>> @@ -168,6 +168,69 @@ struct vm_event_regs_x86 {
>> uint32_t _pad;
>> };
>>
>> +struct vm_event_regs_arm32 {
>> + uint32_t r0;
>> + uint32_t r1;
>> + uint32_t r2;
>> + uint32_t r3;
>> + uint32_t r4;
>> + uint32_t r5;
>> + uint32_t r6;
>> + uint32_t r7;
>> + uint32_t r8;
>> + uint32_t r9;
>> + uint32_t r10;
>> + uint32_t r11;
>> + uint32_t r12;
>> + uint32_t pc;
>> +};
>
> While I had given my v4 comment on the ARM64 variant, I certainly
> meant it to apply here too: I'm missing r13/sp and r14/lr.
Yeap, l've overlooked those. Also, we will need to send TTBCR/TCR_EL1
as well so the guest can properly understand the paging format used by
TTBR0/1..
Tamas
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