>>> On 03.06.16 at 15:26, <jbeul...@suse.com> wrote:
>>>> On 03.06.16 at 14:02, <juwal...@gmail.com> wrote:
>> or is this just some method the overwrite all registers with
>> "ffffffff" first and then set the actual value?
>>
>> [914572] xbk: 06:00.0: write request 4 bytes at 0x10 = ffffffff
>> [914574] xbk: 06:00.0: read 4 bytes at 0x10
>> [914582] xbk: 06:00.0: read 4 bytes at 0x10 = f7a00000
>> [914591] xbk: 06:00.0: read 4 bytes at 0x10
>> [914599] xbk: 06:00.0: read 4 bytes at 0x10 = 10000 <---- fail
>
> That's an unexpected value, indeed (but seems to match up with
> the source, so there's definitely something wrong here - this
> presumably ought to be 0xffff0000, meaning the size of that
> region is 64k).
Mind trying out the attached patch?
Jan
xen-pciback: return proper values during BAR sizing
Reads following writes with all address bits set to 1 should return all
changeable address bits as one, not the BAR size (nor, as was the case
for the upper half of 64-bit BARs, the high half of the region's end
address). Presumably this didn't cause any problems so far because
consumers use the value to calculate the size (usually via val & -val),
and do nothing else with it.
But also consider the exception here: Unimplemented BARs should always
return all zeroes.
And finally, the check for whether to return the sizing address on read
for the ROM BAR should ignore all non-address bits, not just the ROM
Enable one.
Signed-off-by: Jan Beulich <jbeul...@suse.com>
--- head.orig/drivers/xen/xen-pciback/conf_space_header.c 2015-03-16
15:38:59.000000000 +0100
+++ head/drivers/xen/xen-pciback/conf_space_header.c 2016-06-03
15:55:27.629520779 +0200
@@ -149,7 +149,7 @@ static int rom_write(struct pci_dev *dev
/* A write to obtain the length must happen as a 32-bit write.
* This does not (yet) support writing individual bytes
*/
- if (value == ~PCI_ROM_ADDRESS_ENABLE)
+ if ((value | ~PCI_ROM_ADDRESS_MASK) == ~0)
bar->which = 1;
else {
u32 tmpval;
@@ -229,38 +229,42 @@ static inline void read_dev_bar(struct p
(PCI_BASE_ADDRESS_SPACE_MEMORY |
PCI_BASE_ADDRESS_MEM_TYPE_64))) {
bar_info->val = res[pos - 1].start >> 32;
- bar_info->len_val = res[pos - 1].end >> 32;
+ bar_info->len_val = -resource_size(&res[pos - 1]) >> 32;
return;
}
}
+ if (!res[pos].flags ||
+ (res[pos].flags & (IORESOURCE_DISABLED | IORESOURCE_UNSET |
+ IORESOURCE_BUSY)))
+ return;
+
bar_info->val = res[pos].start |
(res[pos].flags & PCI_REGION_FLAG_MASK);
- bar_info->len_val = resource_size(&res[pos]);
+ bar_info->len_val = -resource_size(&res[pos]) |
+ (res[pos].flags & PCI_REGION_FLAG_MASK);
}
static void *bar_init(struct pci_dev *dev, int offset)
{
- struct pci_bar_info *bar = kmalloc(sizeof(*bar), GFP_KERNEL);
+ struct pci_bar_info *bar = kzalloc(sizeof(*bar), GFP_KERNEL);
if (!bar)
return ERR_PTR(-ENOMEM);
read_dev_bar(dev, bar, offset, ~0);
- bar->which = 0;
return bar;
}
static void *rom_init(struct pci_dev *dev, int offset)
{
- struct pci_bar_info *bar = kmalloc(sizeof(*bar), GFP_KERNEL);
+ struct pci_bar_info *bar = kzalloc(sizeof(*bar), GFP_KERNEL);
if (!bar)
return ERR_PTR(-ENOMEM);
read_dev_bar(dev, bar, offset, ~PCI_ROM_ADDRESS_ENABLE);
- bar->which = 0;
return bar;
}
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