Hi Wei, On 26/05/16 08:58, Wei Chen wrote:
Currently, MPIDR_HWID_MASK is using the bit definition of AArch32 MPIDR. From ARMv8 ARM we can see there are 4 levels of affinity on AArch64 whilst AArch32 has only 3. So, this value is not correct when Xen is running on AArch64.Now, we use the value 0xff00ffffff for this macro on AArch64. But neither of this value and its bitwise invert value can be used in mov instruction with the encoding of {imm16:shift} or {imms:immr}. So we have to use ldr to load the bitwise invert value to register. The details of mov immediate encoding are listed in ARMv8 ARM C4.2.5.
The section numbering may change between two versions of the spec. I would mention the version (e.g DDI 0487A.i, I guess?).
Regards, -- Julien Grall _______________________________________________ Xen-devel mailing list Xen-devel@lists.xen.org http://lists.xen.org/xen-devel
